1:26:41 Remoticon 2020 // Zero to ASIC: Silicon Design with Skywater-PDK HACKADAY 36.1K views - 5 years ago
1:09:41 0. ASIC & RTL Design Flow Explained | Digital Design Fundamentals #30daysofverilog Anish Saha and PrepFusion - GATE 17.9K views - 1 year ago
22:08 How does a flip flop work, what is metastability and why does it have setup & hold time? Zero To ASIC Course 11.3K views - 4 years ago
21:46 The ULTIMATE VLSI ROADMAP 2026| How to get into semiconductor industry? | Ece Roadmap! Sanchit Kulkarni 488.8K views - 1 year ago
55:04 Computer & Technology Basics Course for Absolute Beginners freeCodeCamp.org 6.5M views - 3 years ago
37:13 FPGA from Zero to Hero - Live & Free Courses 3/28 (English Version) False Paths 1.5K views - 1 year ago
7:14:30 Ethical Hacking in 15 Hours - 2023 Edition - Learn to Hack! (Part 1) The Cyber Mentor 3.9M views - 3 years ago
4:06 The Zero ASIC Issue Explained: What You Need to Know about S17+ Hashboards D-Central 548 views - 3 years ago
2:51:30 Antminer S19j Pro "0 ASIC" Repair - Bitcoin ASIC Miner Repair LIVE - 022 D-Central 7.2K views - 3 years ago
33:27 VLSI RTL Design Mock Interview | For Freshers & Entry-Level Jobs | prasanthi Chanda ProV Logic 65.7K views - 10 months ago
23:22:20 Data Science Full Course 2026 [FREE] | Learn Data Science From Scratch in 24 Hours | Simplilearn Simplilearn 81.5K views - 4 months ago
28:41 FPGA Design Tutorial (Verilog, Simulation, Implementation) - Phil's Lab #109 Phil’s Lab 128.2K views - 3 years ago