FPGA Developers' Forum

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The FPGA Developers’ Forum (FDF) is a platform to discuss and exchange information, experiences, implementation ideas, tips, and tricks as well as challenges faced with design tools, specific FPGA technologies. So far, the forum consists of a Discourse online forum, a newsletter, recurrent seminars and an annual meeting.

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DevOps for FPGA 101: from version control to hardware in the loop testing (Matteo Vit)

DevOps for FPGA 101: from version control to hardware in the loop testing (Matteo Vit) FPGA Developers' Forum

33 views - 1 day ago

fwk: An Open Source Framework for Standardized FPGA Development at DESY (Cagil Gumus)

fwk: An Open Source Framework for Standardized FPGA Development at DESY (Cagil Gumus) FPGA Developers' Forum

47 views - 2 days ago

VHDL LS: A Free and Open Source Language Server for VHDL (Lukas Scheller)

VHDL LS: A Free and Open Source Language Server for VHDL (Lukas Scheller) FPGA Developers' Forum

88 views - 3 days ago

Dynamic Derandomizing Buffer: A portable Solution for Time Ordered Packet Aggregation (Mitja Vodnik)

Dynamic Derandomizing Buffer: A portable Solution for Time Ordered Packet Aggregation (Mitja Vodnik) FPGA Developers' Forum

47 views - 4 days ago

Study of non linearities on the AMD Phase Interpolator (Edoardo Orzes)

Study of non linearities on the AMD Phase Interpolator (Edoardo Orzes) FPGA Developers' Forum

34 views - 5 days ago

Hi speed digital twins: Pushing sim time steps into the ns range using Versal ACAP (Pablo Trujillo)

Hi speed digital twins: Pushing sim time steps into the ns range using Versal ACAP (Pablo Trujillo) FPGA Developers' Forum

148 views - 6 days ago

Accelerating Data: Lossless Compression in FPGA(Calliope-Louisa Sotiropoulou)

Accelerating Data: Lossless Compression in FPGA(Calliope-Louisa Sotiropoulou) FPGA Developers' Forum

125 views - 1 week ago

NGRC on SoC for online learning of dynamical systems (João Folhadela)

NGRC on SoC for online learning of dynamical systems (João Folhadela) FPGA Developers' Forum

79 views - 1 week ago

HGQ: High Granularity Quantization for Real time Neural Networks and LUT Based Inference (Chang Su)

HGQ: High Granularity Quantization for Real time Neural Networks and LUT Based Inference (Chang Su) FPGA Developers' Forum

81 views - 1 week ago

KalEdge Lite: Hardware Aware ML to FPGA Deployment with Automated hls4ml Integration (Romina Soled)

KalEdge Lite: Hardware Aware ML to FPGA Deployment with Automated hls4ml Integration (Romina Soled) FPGA Developers' Forum

99 views - 1 week ago

Open Source HDL Co Simulation with AMD Alveo (Matthias Kern)

Open Source HDL Co Simulation with AMD Alveo (Matthias Kern) FPGA Developers' Forum

138 views - 1 week ago

AMD Embedded AI Solutions (Thomas Gmeinder)

AMD Embedded AI Solutions (Thomas Gmeinder) FPGA Developers' Forum

91 views - 1 week ago

Open source simulation landscape and advances towards mixed language support (Augusto Fraga Giach)

Open source simulation landscape and advances towards mixed language support (Augusto Fraga Giach) FPGA Developers' Forum

135 views - 2 weeks ago

Inside UVVM: Architecture and Design of Custom Verification Components (Markus Leiter)

Inside UVVM: Architecture and Design of Custom Verification Components (Markus Leiter) FPGA Developers' Forum

67 views - 2 weeks ago

USB implementation with GateMate FPGA (Anton Kuzmin)

USB implementation with GateMate FPGA (Anton Kuzmin) FPGA Developers' Forum

250 views - 2 weeks ago

NDK framework: Deep Diving into High Throughput Network Monitoring Pipelines (Daniel Kondys)

NDK framework: Deep Diving into High Throughput Network Monitoring Pipelines (Daniel Kondys) FPGA Developers' Forum

51 views - 2 weeks ago

The PoC Library: Free and Open Source VHDL IP Core Library (Patrick Lehmann)

The PoC Library: Free and Open Source VHDL IP Core Library (Patrick Lehmann) FPGA Developers' Forum

192 views - 2 weeks ago

Scalable and lightweight RoCEv2 TX FPGA IP core (Gabriele Bortolato)

Scalable and lightweight RoCEv2 TX FPGA IP core (Gabriele Bortolato) FPGA Developers' Forum

142 views - 2 weeks ago

What Star Trek can teach us about using AI in FPGA design (Adam Taylor)

What Star Trek can teach us about using AI in FPGA design (Adam Taylor) FPGA Developers' Forum

274 views - 2 weeks ago

Introduction to FDF26 (Davide Cieri)

Introduction to FDF26 (Davide Cieri) FPGA Developers' Forum

55 views - 2 weeks ago

GateMate: A European 28nm FPGA with an Open-Source Toolchain and Radiation Qualification Results

GateMate: A European 28nm FPGA with an Open-Source Toolchain and Radiation Qualification Results FPGA Developers' Forum

596 views - 8 months ago

Practical Methods for Functional Verification

Practical Methods for Functional Verification FPGA Developers' Forum

87 views - 1 year ago

HDLRegression: A reliable and efficient tool for FPGA regression testing

HDLRegression: A reliable and efficient tool for FPGA regression testing FPGA Developers' Forum

64 views - 1 year ago

Where Innovation Meets Reliability – FPGA based solutions by Trenz Electronic

Where Innovation Meets Reliability – FPGA based solutions by Trenz Electronic FPGA Developers' Forum

92 views - 1 year ago

NDK: An open-source framework for high-speed network applications on FPGAs

NDK: An open-source framework for high-speed network applications on FPGAs FPGA Developers' Forum

88 views - 1 year ago

Disruptive Efinix Quantum Architecture

Disruptive Efinix Quantum Architecture FPGA Developers' Forum

229 views - 1 year ago

Low Jitter Frame Clock Recovery in Xilinx Ultrascale+ Transceivers

Low Jitter Frame Clock Recovery in Xilinx Ultrascale+ Transceivers FPGA Developers' Forum

292 views - 1 year ago

High Performance FPGA Solutions – PRO DESIGN, best Choice for Development and Manufacturing

High Performance FPGA Solutions – PRO DESIGN, best Choice for Development and Manufacturing FPGA Developers' Forum

57 views - 1 year ago

Implementation of TDC on FPGA for high-resolution-performance in Particle Therapy applications

Implementation of TDC on FPGA for high-resolution-performance in Particle Therapy applications FPGA Developers' Forum

454 views - 1 year ago

Accelerating Transformer Neural Networks on FPGAs for High Energy Physics Experiments

Accelerating Transformer Neural Networks on FPGAs for High Energy Physics Experiments FPGA Developers' Forum

271 views - 1 year ago

Get the right FPGA quality through efficient Requirements Coverage (aka Specification Coverage)

Get the right FPGA quality through efficient Requirements Coverage (aka Specification Coverage) FPGA Developers' Forum

39 views - 1 year ago

Chisel4ml: Fast Implementations of Deeply Quantized Neural Networks using Chisel Generators

Chisel4ml: Fast Implementations of Deeply Quantized Neural Networks using Chisel Generators FPGA Developers' Forum

68 views - 1 year ago

Abstract interface modelling for better genericity and code clarity

Abstract interface modelling for better genericity and code clarity FPGA Developers' Forum

37 views - 1 year ago

Architecting FPGA for low power Leadership

Architecting FPGA for low power Leadership FPGA Developers' Forum

45 views - 1 year ago

Application-Specific Arithmetic Operators with the FloPoCo HDL core generator

Application-Specific Arithmetic Operators with the FloPoCo HDL core generator FPGA Developers' Forum

88 views - 1 year ago

Unleashing 100G Performance: High-Speed UDP/TCP Hardware Stacks for FPGAs by CAST

Unleashing 100G Performance: High-Speed UDP/TCP Hardware Stacks for FPGAs by CAST FPGA Developers' Forum

195 views - 1 year ago

Generating memory maps with Cheby and Reksio

Generating memory maps with Cheby and Reksio FPGA Developers' Forum

86 views - 1 year ago

Exploring Linearity and Temperature Stability in Time-to-Digital Converters

Exploring Linearity and Temperature Stability in Time-to-Digital Converters FPGA Developers' Forum

52 views - 1 year ago

Python-based, flexible testbench for a spacecraft payload

Python-based, flexible testbench for a spacecraft payload FPGA Developers' Forum

60 views - 1 year ago

Standardizing SoC Development in CERN's accelerator complex: A Build System for Xilinx Platforms

Standardizing SoC Development in CERN's accelerator complex: A Build System for Xilinx Platforms FPGA Developers' Forum

50 views - 1 year ago

The PandABlocks framework for flexible run-time configuration of Zynq SoCs

The PandABlocks framework for flexible run-time configuration of Zynq SoCs FPGA Developers' Forum

56 views - 1 year ago

Error-Redundant Implementation of Commercial IP Cores: A Practical Example

Error-Redundant Implementation of Commercial IP Cores: A Practical Example FPGA Developers' Forum

35 views - 1 year ago

YosysHQ - Building alternative FPGA toolchains

YosysHQ - Building alternative FPGA toolchains FPGA Developers' Forum

355 views - 1 year ago

Customized eFPGAs with FABulous

Customized eFPGAs with FABulous FPGA Developers' Forum

38 views - 1 year ago

Allo: A Python-Embedded Programming Model for Composable Accelerator Design

Allo: A Python-Embedded Programming Model for Composable Accelerator Design FPGA Developers' Forum

37 views - 1 year ago

A Reconfigurable FPGA-Based ML Library for Kernel Methods

A Reconfigurable FPGA-Based ML Library for Kernel Methods FPGA Developers' Forum

52 views - 1 year ago

A low latency Gated Recurrent Unit Implementation for the AMD Versal AI Engine

A low latency Gated Recurrent Unit Implementation for the AMD Versal AI Engine FPGA Developers' Forum

180 views - 1 year ago

Why Your Team Should be using VHDL + OSVVM for Verification

Why Your Team Should be using VHDL + OSVVM for Verification FPGA Developers' Forum

255 views - 1 year ago

FPGA Implementation of Next-Generation Reservoir Computing for predicting dynamical systems

FPGA Implementation of Next-Generation Reservoir Computing for predicting dynamical systems FPGA Developers' Forum

136 views - 1 year ago

Open Logic – open-source FPGA Standard Library

Open Logic – open-source FPGA Standard Library FPGA Developers' Forum

137 views - 1 year ago

Welcome to the 2nd FPGA Developers' Forum

Welcome to the 2nd FPGA Developers' Forum FPGA Developers' Forum

179 views - 1 year ago

S. Baron: The future of FPGAs in HEP detectors for FCC and beyond

S. Baron: The future of FPGAs in HEP detectors for FCC and beyond FPGA Developers' Forum

51 views - 1 year ago

Welcome to CERN

Welcome to CERN FPGA Developers' Forum

76 views - 1 year ago

Distributed Arithmetic for Real-time Neural Networks on FPGAs

Distributed Arithmetic for Real-time Neural Networks on FPGAs FPGA Developers' Forum

133 views - 1 year ago

Innovative FPGA Customization Tools for High-Speed Data Processing in Physics Experiments

Innovative FPGA Customization Tools for High-Speed Data Processing in Physics Experiments FPGA Developers' Forum

148 views - 1 year ago

Hog (HDL on git) Tutorial 2025: Part II Create and Manage an HDL repository with Hog

Hog (HDL on git) Tutorial 2025: Part II Create and Manage an HDL repository with Hog FPGA Developers' Forum

317 views - 1 year ago

Hog (HDL on git) Tutorial 2025: Part I Hog Introduction

Hog (HDL on git) Tutorial 2025: Part I Hog Introduction FPGA Developers' Forum

613 views - 1 year ago

Hog (HDL on Git) Tutorial Part 3. Hog advanced features: Hog logger and complex projects¶

Hog (HDL on Git) Tutorial Part 3. Hog advanced features: Hog logger and complex projects¶ FPGA Developers' Forum

66 views - 1 year ago

M. Barbanera - The FPGA design for the L0 trigger of the RICH detector of the NA62 Experiment

M. Barbanera - The FPGA design for the L0 trigger of the RICH detector of the NA62 Experiment FPGA Developers' Forum

81 views - 1 year ago

D. Radocon: Smash HDL bugs on the fly!

D. Radocon: Smash HDL bugs on the fly! FPGA Developers' Forum

128 views - 1 year ago