bustedwing

@UCAjGXqFb2IwurkOR5cHDOGA - 101 subscribers

I know, I know... the video quality is horrible and the audio is worse. This channel is meant to be a quick and dirty video notebook to help jog my memory. If I spend more time on video then I'll be spending less time doing what I actual want to be doing. So it's a tradeoff, more terrible video... or less quality video. If you happen to get anything useful out of these videos... I'd be happy to hear about it. And if you have a better way of doing something, I'd love to hear that too. I recommend watching at 1.75x or faster. Best Regards, BW.

Home Videos Live Playlists

BeagleV Fire 8c Starting RISC V ASM on SERV

BeagleV Fire 8c Starting RISC V ASM on SERV bustedwing

184 views - 1 year ago

BeagleV Fire 8b Hacking SERV ant Verilog

BeagleV Fire 8b Hacking SERV ant Verilog bustedwing

92 views - 1 year ago

BeagleV Fire 8a Investigate LEDs with Libero

BeagleV Fire 8a Investigate LEDs with Libero bustedwing

191 views - 1 year ago

BeagleV Fire 7a VHDL on Fire FPGA

BeagleV Fire 7a VHDL on Fire FPGA bustedwing

183 views - 1 year ago

Beagle Fire 6c SERV RISC V in Gateware Programmed by MSS

Beagle Fire 6c SERV RISC V in Gateware Programmed by MSS bustedwing

163 views - 1 year ago

BeagleV Fire 6c SERV RISCV with APB Loading Program from MSS TLDR

BeagleV Fire 6c SERV RISCV with APB Loading Program from MSS TLDR bustedwing

107 views - 1 year ago

BeagleV Fire 6b Verilog Data Capture FIFO

BeagleV Fire 6b Verilog Data Capture FIFO bustedwing

130 views - 1 year ago

BeagleV Fire 6a Read Write RAM in CAPE over APB MSS RISC V Processors

BeagleV Fire 6a Read Write RAM in CAPE over APB MSS RISC V Processors bustedwing

176 views - 1 year ago

BeagleV Fire 5a View Push Buttons in Libero

BeagleV Fire 5a View Push Buttons in Libero bustedwing

347 views - 1 year ago

BeagleV Fire 4b Processor Read Write to Gateware

BeagleV Fire 4b Processor Read Write to Gateware bustedwing

297 views - 1 year ago

BeagleV Fire 4a Processor Read Write to Gateware

BeagleV Fire 4a Processor Read Write to Gateware bustedwing

145 views - 1 year ago

BeagleV Fire 3b Investigate your design with Libero

BeagleV Fire 3b Investigate your design with Libero bustedwing

207 views - 1 year ago

BeagleV Fire 3a Build on Windows with Git Bash

BeagleV Fire 3a Build on Windows with Git Bash bustedwing

181 views - 1 year ago

BeagleV Fire 2a Gateware SERV on Fire

BeagleV Fire 2a Gateware SERV on Fire bustedwing

168 views - 1 year ago

BeagleV Fire 1b Deploy FPGA Image to Board

BeagleV Fire 1b Deploy FPGA Image to Board bustedwing

248 views - 1 year ago

BeagleV Fire Gateware 1a Fork Customize Build

BeagleV Fire Gateware 1a Fork Customize Build bustedwing

318 views - 1 year ago

BeagleV Fire Gateware 0 Getting Started FAILED ATTEMPT

BeagleV Fire Gateware 0 Getting Started FAILED ATTEMPT bustedwing

291 views - 1 year ago

sed awk intel hex to readmemh

sed awk intel hex to readmemh bustedwing

14 views - 1 year ago

RISCV Stuff 1 Install Script for the RISCV GNU Toolchain

RISCV Stuff 1 Install Script for the RISCV GNU Toolchain bustedwing

613 views - 1 year ago

Polarfire Icicle 9h Use uPROM 470 bits not bytes declare success

Polarfire Icicle 9h Use uPROM 470 bits not bytes declare success bustedwing

31 views - 1 year ago

Polarfire Icicle 9g Use uPROM to initialize LSRAM 4 fail

Polarfire Icicle 9g Use uPROM to initialize LSRAM 4 fail bustedwing

9 views - 1 year ago

Polarfire Icicle 9f Use uPROM to initialize LSRAM 3 Fail

Polarfire Icicle 9f Use uPROM to initialize LSRAM 3 Fail bustedwing

21 views - 1 year ago

Polarfire Icicle 9e Use uPROM to initialize LSRAM 2 Fail

Polarfire Icicle 9e Use uPROM to initialize LSRAM 2 Fail bustedwing

17 views - 1 year ago

Polarfire Icicle 9d Use uPROM to initialiize LSRAM 1 fail

Polarfire Icicle 9d Use uPROM to initialiize LSRAM 1 fail bustedwing

2 views - 1 year ago

Polarfire Icicle 9c Increase AXI LSRAM Address Space

Polarfire Icicle 9c Increase AXI LSRAM Address Space bustedwing

37 views - 1 year ago

Polarfire Icicle 9b Using too much sNVM Error

Polarfire Icicle 9b Using too much sNVM Error bustedwing

39 views - 1 year ago

Polarfire Icicle 9a Initialize AXI LSRAM Libero

Polarfire Icicle 9a Initialize AXI LSRAM Libero bustedwing

49 views - 1 year ago

Polarfire Icicle 8 - MSS access FPGA Block RAM with AXI

Polarfire Icicle 8 - MSS access FPGA Block RAM with AXI bustedwing

149 views - 2 years ago

Polarfire Icicle 7 Success Bare Metal read writes of fpga

Polarfire Icicle 7 Success Bare Metal read writes of fpga bustedwing

69 views - 2 years ago

Polarfire Icicle 6 Processor read write to FPGA Verilog block

Polarfire Icicle 6 Processor read write to FPGA Verilog block bustedwing

26 views - 2 years ago

Polarfire Icicle 3 Raspberry Pi Connector

Polarfire Icicle 3 Raspberry Pi Connector bustedwing

69 views - 2 years ago

Polarfire Icicle 5 Libero add debug pins

Polarfire Icicle 5 Libero add debug pins bustedwing

59 views - 2 years ago

Polarfire Icicle 4 Program FPGA FlashPro

Polarfire Icicle 4 Program FPGA FlashPro bustedwing

80 views - 2 years ago

polarfire Icicle 2 Connect FPGA to Microbus SPI with Libero

polarfire Icicle 2 Connect FPGA to Microbus SPI with Libero bustedwing

128 views - 2 years ago

Polarfire Icicle 1 Struggle to find Mikrobus SPI

Polarfire Icicle 1 Struggle to find Mikrobus SPI bustedwing

120 views - 2 years ago

Run RISC V Processor on FPGA part 3 Success

Run RISC V Processor on FPGA part 3 Success bustedwing

75 views - 2 years ago

Low Disk Space Linux Tools to find Diskspace Hogs

Low Disk Space Linux Tools to find Diskspace Hogs bustedwing

5 views - 2 years ago

intro to Sed Stream Editor with Examples

intro to Sed Stream Editor with Examples bustedwing

11 views - 2 years ago

Virtualbox Setup Shared Folder

Virtualbox Setup Shared Folder bustedwing

17 views - 2 years ago

Run RISC-V Processor on FPGA - Part 2 Synthesis

Run RISC-V Processor on FPGA - Part 2 Synthesis bustedwing

181 views - 2 years ago

Run RISC V Processor on FPGA Part 1 Get the Verilog

Run RISC V Processor on FPGA Part 1 Get the Verilog bustedwing

266 views - 2 years ago

2 Getting Blinky to Simulate with RISC V SERV

2 Getting Blinky to Simulate with RISC V SERV bustedwing

47 views - 2 years ago

GitHub My First Pull Request

GitHub My First Pull Request bustedwing

6 views - 2 years ago

Delete Section of Video with ClipChamp

Delete Section of Video with ClipChamp bustedwing

61 views - 2 years ago

1 Getting Started with RISC-V SERV Processor

1 Getting Started with RISC-V SERV Processor bustedwing

502 views - 2 years ago

VHDL 1 - Intro to GHDL and GTKWave

VHDL 1 - Intro to GHDL and GTKWave bustedwing

329 views - 2 years ago

Verilog vs VHDL Side by Side HDL Comparison

Verilog vs VHDL Side by Side HDL Comparison bustedwing

286 views - 2 years ago

FPGA Polarfire Icicle Libero Part 7 PuTTY controls Blinky

FPGA Polarfire Icicle Libero Part 7 PuTTY controls Blinky bustedwing

238 views - 2 years ago

FPGA Polarfire Icicle Libero Part 6b C Blinky Sucess

FPGA Polarfire Icicle Libero Part 6b C Blinky Sucess bustedwing

248 views - 2 years ago

FPGA Polarfire Icicle Libero Part 6 C code to Control Gateware Fabric

FPGA Polarfire Icicle Libero Part 6 C code to Control Gateware Fabric bustedwing

366 views - 2 years ago

FPGA Polarfire Icicle Libero Part 5 Blinky Success

FPGA Polarfire Icicle Libero Part 5 Blinky Success bustedwing

382 views - 2 years ago

FPGA Polarfire Icicle Libero Part 4 - Add Custom Verilog

FPGA Polarfire Icicle Libero Part 4 - Add Custom Verilog bustedwing

483 views - 2 years ago

FPGA Polarfire Icicle Libero Part 3 - Program the FPGA

FPGA Polarfire Icicle Libero Part 3 - Program the FPGA bustedwing

536 views - 2 years ago

FPGA Polarfire Icicle Libero Part 2 - Synthesize and Generate Bitstream

FPGA Polarfire Icicle Libero Part 2 - Synthesize and Generate Bitstream bustedwing

643 views - 2 years ago

FPGA Polarfire Icicle Libero Part 1 - Build the Reference Design

FPGA Polarfire Icicle Libero Part 1 - Build the Reference Design bustedwing

872 views - 2 years ago

FPGA Polarfire Icicle Libero Part 0 - Softconsole Bare Metal UART PuTTY demo

FPGA Polarfire Icicle Libero Part 0 - Softconsole Bare Metal UART PuTTY demo bustedwing

1.9K views - 2 years ago

Verilog Testbench for Blinky with APB

Verilog Testbench for Blinky with APB bustedwing

24 views - 2 years ago

Verilog Blinky with APB Interface

Verilog Blinky with APB Interface bustedwing

31 views - 2 years ago

APB Simulation with iVerilog and GTKWave

APB Simulation with iVerilog and GTKWave bustedwing

28 views - 2 years ago

APB Processor to FPGA Interface

APB Processor to FPGA Interface bustedwing

83 views - 2 years ago