Abhijit Pethe

@UCJYo6_GHggS9R9mnD_a5MqA - 872 subscribers

Semiconductors, VLSI, and circuit design — explained from first principles with engineering depth. Deep-dive lectures on semiconductor devices, VLSI design, and chip engineering — built for students and working engineers who want real understanding, not surface-level definitions. 15 years in the semiconductor industry. Start with the 'Start Here' playlist if you're new

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Why Transistors Behave the Way They Do (Beyond the “Switch” Model)

Why Transistors Behave the Way They Do (Beyond the “Switch” Model) Abhijit Pethe

26 views - 2 days ago

Why Transistors Age: NBTI, Reliability Physics & Lifetime Prediction Explained

Why Transistors Age: NBTI, Reliability Physics & Lifetime Prediction Explained Abhijit Pethe

30 views - 4 days ago

Why Scaling Is Getting Harder (Yield, Variation, Device Physics)

Why Scaling Is Getting Harder (Yield, Variation, Device Physics) Abhijit Pethe

14 views - 1 week ago

Timing Closure Explained: How Engineers Fix Negative Slack (STA Final Step)

Timing Closure Explained: How Engineers Fix Negative Slack (STA Final Step) Abhijit Pethe

33 views - 1 week ago

Why Timing Fails: Clock Skew, Jitter, and Clock Trees Explained

Why Timing Fails: Clock Skew, Jitter, and Clock Trees Explained Abhijit Pethe

60 views - 1 week ago

Interconnect Delay Explained | Why Wires Dominate Timing in Modern Chips (STA Basics)

Interconnect Delay Explained | Why Wires Dominate Timing in Modern Chips (STA Basics) Abhijit Pethe

59 views - 2 weeks ago

Why Wires Matter More Than Transistors (Modern Chips Explained)

Why Wires Matter More Than Transistors (Modern Chips Explained) Abhijit Pethe

87 views - 2 weeks ago

Why CPU Clock Speeds Stopped Increasing (Power Explained)

Why CPU Clock Speeds Stopped Increasing (Power Explained) Abhijit Pethe

130 views - 2 weeks ago

Faster Gates Leak More?! | LVT vs SVT vs HVT Explained

Faster Gates Leak More?! | LVT vs SVT vs HVT Explained Abhijit Pethe

110 views - 2 weeks ago

Why Chips Aren’t Bigger (Yield Explained in Simple Terms)

Why Chips Aren’t Bigger (Yield Explained in Simple Terms) Abhijit Pethe

28 views - 3 weeks ago

Why Setup Fails at SS and Hold Fails at FF | PVT Corners Explained

Why Setup Fails at SS and Hold Fails at FF | PVT Corners Explained Abhijit Pethe

114 views - 3 weeks ago

Why Slowing the Clock Doesn’t Fix Hold Violations

Why Slowing the Clock Doesn’t Fix Hold Violations Abhijit Pethe

98 views - 3 weeks ago

Why Chips Work Even When Everything Is Wrong

Why Chips Work Even When Everything Is Wrong Abhijit Pethe

74 views - 3 weeks ago

Why Timing Gets Worse After Layout | Setup Violations Explained

Why Timing Gets Worse After Layout | Setup Violations Explained Abhijit Pethe

109 views - 3 weeks ago

Why “Correct” Chip Designs Still Fail (Variation Explained)

Why “Correct” Chip Designs Still Fail (Variation Explained) Abhijit Pethe

29 views - 4 weeks ago

Why Chips Fail Timing (Even When Logic Is Correct) | STA Explained

Why Chips Fail Timing (Even When Logic Is Correct) | STA Explained Abhijit Pethe

134 views - 4 weeks ago

Why a Small Layout Change Can Kill Your Chip (Real Silicon Explained)

Why a Small Layout Change Can Kill Your Chip (Real Silicon Explained) Abhijit Pethe

95 views - 4 weeks ago

Why Smaller Transistors Stopped Making Chips Faster

Why Smaller Transistors Stopped Making Chips Faster Abhijit Pethe

152 views - 1 month ago

Why SRAM Is So Hard to Design (6T Bitcell Explained)

Why SRAM Is So Hard to Design (6T Bitcell Explained) Abhijit Pethe

92 views - 1 month ago

The Computer You Think You’re Using Doesn’t Exist | What Computer Architecture Really Is

The Computer You Think You’re Using Doesn’t Exist | What Computer Architecture Really Is Abhijit Pethe

103 views - 1 month ago

Why Chips Still Use Copper Instead of Light

Why Chips Still Use Copper Instead of Light Abhijit Pethe

115 views - 1 month ago

Why Transistors Can’t Shrink Forever | Quantum Limits of CMOS Scaling

Why Transistors Can’t Shrink Forever | Quantum Limits of CMOS Scaling Abhijit Pethe

59 views - 1 month ago

Why CPU Clock Speeds Stopped Increasing | The Power Wall & End of Dennard Scaling Explained

Why CPU Clock Speeds Stopped Increasing | The Power Wall & End of Dennard Scaling Explained Abhijit Pethe

175 views - 1 month ago

Why Your CPU Never Reaches Peak FLOPs (Memory Wall Explained)

Why Your CPU Never Reaches Peak FLOPs (Memory Wall Explained) Abhijit Pethe

71 views - 1 month ago

Why MOS Inversion Charge Is Not at the Interface | Quantum Well Explained

Why MOS Inversion Charge Is Not at the Interface | Quantum Well Explained Abhijit Pethe

69 views - 1 month ago

Laplace Transform for Engineers (Part 7) | Advanced Non-Textbook RLC Systems

Laplace Transform for Engineers (Part 7) | Advanced Non-Textbook RLC Systems Abhijit Pethe

41 views - 1 month ago

Stability in Feedback Amplifiers Explained | Loop Gain, Nyquist, Phase Margin & Compensation

Stability in Feedback Amplifiers Explained | Loop Gain, Nyquist, Phase Margin & Compensation Abhijit Pethe

147 views - 1 month ago

Laplace Transform for Engineers (Part 6) | Pulses, Pulse Trains, Sawtooth in s-Domain

Laplace Transform for Engineers (Part 6) | Pulses, Pulse Trains, Sawtooth in s-Domain Abhijit Pethe

16 views - 1 month ago

Laplace Transform for Engineers (Part 5) | Impulse, Step, Ramp in the s-Domain

Laplace Transform for Engineers (Part 5) | Impulse, Step, Ramp in the s-Domain Abhijit Pethe

33 views - 1 month ago

Laplace Transform for Engineers (Part 4) | Frequency Response Explained as H(jω)

Laplace Transform for Engineers (Part 4) | Frequency Response Explained as H(jω) Abhijit Pethe

46 views - 1 month ago

Laplace Transform for Engineers (Part 3) | Transfer Functions, Poles, and Zeros

Laplace Transform for Engineers (Part 3) | Transfer Functions, Poles, and Zeros Abhijit Pethe

26 views - 1 month ago

Laplace Transform for Engineers (Part 2) | State, Order, and Modes in the s-Domain

Laplace Transform for Engineers (Part 2) | State, Order, and Modes in the s-Domain Abhijit Pethe

22 views - 1 month ago

Laplace Transform for Engineers (Part 1) | s-Domain Modeling for RLC Circuits

Laplace Transform for Engineers (Part 1) | s-Domain Modeling for RLC Circuits Abhijit Pethe

55 views - 3 months ago

First-Order Circuits Explained Properly | RC & RL Transients Beyond Textbook Step Responses

First-Order Circuits Explained Properly | RC & RL Transients Beyond Textbook Step Responses Abhijit Pethe

157 views - 3 months ago

Thevenin & Norton Theorems Explained Clearly | Linearity, Dependent Sources & Maximum Power Transfer

Thevenin & Norton Theorems Explained Clearly | Linearity, Dependent Sources & Maximum Power Transfer Abhijit Pethe

77 views - 3 months ago

KCL and KVL Explained from First Principles | Nodal and Mesh Analysis Intuition

KCL and KVL Explained from First Principles | Nodal and Mesh Analysis Intuition Abhijit Pethe

305 views - 3 months ago

Why Silicon Oxidizes | Thermal Oxidation and the Deal–Grove Model Explained

Why Silicon Oxidizes | Thermal Oxidation and the Deal–Grove Model Explained Abhijit Pethe

233 views - 3 months ago

Why Depletion Regions Form | PN Junction Physics, Built-In Voltage & Electric Fields

Why Depletion Regions Form | PN Junction Physics, Built-In Voltage & Electric Fields Abhijit Pethe

77 views - 4 months ago

Why Band Diagrams Matter | Understanding Semiconductor Devices from First Principles

Why Band Diagrams Matter | Understanding Semiconductor Devices from First Principles Abhijit Pethe

82 views - 4 months ago

Why Some CMOS Gates Are Harder to Design | Logical Effort & Delay Explained

Why Some CMOS Gates Are Harder to Design | Logical Effort & Delay Explained Abhijit Pethe

718 views - 4 months ago

CMOS Inverter Delay, Noise Margins & Transmission Gates | VLSI Design Problem Solving Tutorial

CMOS Inverter Delay, Noise Margins & Transmission Gates | VLSI Design Problem Solving Tutorial Abhijit Pethe

251 views - 4 months ago

MOSFET Problem Solving Tutorial | EOT, Threshold Voltage, C–V Analysis and Velocity Saturation

MOSFET Problem Solving Tutorial | EOT, Threshold Voltage, C–V Analysis and Velocity Saturation Abhijit Pethe

105 views - 5 months ago

Schottky Diodes and MOS C–V Analysis Explained | Barrier Height, Work Func. & Oxide Charge Tutorial

Schottky Diodes and MOS C–V Analysis Explained | Barrier Height, Work Func. & Oxide Charge Tutorial Abhijit Pethe

91 views - 5 months ago

PN Junction Diode Problems Explained | Built-In Voltage, SatCurrent , Depletion Width Tutorial

PN Junction Diode Problems Explained | Built-In Voltage, SatCurrent , Depletion Width Tutorial Abhijit Pethe

110 views - 5 months ago

PN Junction Diode Problem Solving Tutorial | Built-In Voltage, Saturation Current & Depletion Width

PN Junction Diode Problem Solving Tutorial | Built-In Voltage, Saturation Current & Depletion Width Abhijit Pethe

45 views - 5 months ago

Electronic Devices Problem Solving | Electric Field, Carrier Lifetime and Photoconductors Explained

Electronic Devices Problem Solving | Electric Field, Carrier Lifetime and Photoconductors Explained Abhijit Pethe

62 views - 5 months ago

Why Your FSM Output Depends on When You Ask | Moore vs Mealy State Machines Explained

Why Your FSM Output Depends on When You Ask | Moore vs Mealy State Machines Explained Abhijit Pethe

411 views - 7 months ago

Why Two Identical Chips Behave Differently | Monte Carlo Analysis, Yield and Variation in VLSI

Why Two Identical Chips Behave Differently | Monte Carlo Analysis, Yield and Variation in VLSI Abhijit Pethe

565 views - 8 months ago

Cascode Amplifiers & Current Mirrors Tutorial | Design Problems, Gain & Output Resistance Explained

Cascode Amplifiers & Current Mirrors Tutorial | Design Problems, Gain & Output Resistance Explained Abhijit Pethe

340 views - 8 months ago

Common Gate and Source Follower Amplifiers Explained | Gain, Impedance and Buffer Operation

Common Gate and Source Follower Amplifiers Explained | Gain, Impedance and Buffer Operation Abhijit Pethe

289 views - 8 months ago

Common Source Amplifier Explained (Step-by-Step) | Gain, Biasing, gm & ro Intuition

Common Source Amplifier Explained (Step-by-Step) | Gain, Biasing, gm & ro Intuition Abhijit Pethe

410 views - 8 months ago

Verilog HDL: Parameters, Generate Blocks & Professional Testbenches

Verilog HDL: Parameters, Generate Blocks & Professional Testbenches Abhijit Pethe

158 views - 9 months ago

Verilog Sequential Logic Explained: always_ff, always_comb, Latches and FSM Design

Verilog Sequential Logic Explained: always_ff, always_comb, Latches and FSM Design Abhijit Pethe

200 views - 9 months ago

Verilog HDL Basics: Modules, Operators, Assign, Delays and Structural Modeling

Verilog HDL Basics: Modules, Operators, Assign, Delays and Structural Modeling Abhijit Pethe

323 views - 10 months ago

Why DRAM Forgets Everything Unless You Keep Refreshing It | 1T1C Cell and Sense Amplifiers Explained

Why DRAM Forgets Everything Unless You Keep Refreshing It | 1T1C Cell and Sense Amplifiers Explained Abhijit Pethe

400 views - 10 months ago

What a PDK Actually Contains | The Kit That Makes Chip Design Possible

What a PDK Actually Contains | The Kit That Makes Chip Design Possible Abhijit Pethe

1.3K views - 10 months ago

Why No Amount of Extra Time Guarantees a Flip-Flop Will Decide | Metastability Explained

Why No Amount of Extra Time Guarantees a Flip-Flop Will Decide | Metastability Explained Abhijit Pethe

310 views - 10 months ago

Shunt–Series Feedback | Current Amplifiers, Loop Gain & Resistance Control

Shunt–Series Feedback | Current Amplifiers, Loop Gain & Resistance Control Abhijit Pethe

544 views - 11 months ago

Shunt–Shunt Feedback | Transresistance Amplifiers, Loop Gain & Resistance Reduction

Shunt–Shunt Feedback | Transresistance Amplifiers, Loop Gain & Resistance Reduction Abhijit Pethe

386 views - 11 months ago

Series–Series Feedback Explained | Transconductance Amplifiers, Loop Gain & Resistance Effects

Series–Series Feedback Explained | Transconductance Amplifiers, Loop Gain & Resistance Effects Abhijit Pethe

375 views - 11 months ago