Advanced Engineering Radar Systems

@UCMwD0lz3DqF4hRoScDofW1w - 2.3K subscribers

Channel about Radar Signal and Data processing, algorithms implementation and analysis. For more details, please visit my website www.fpga-radar.com/

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MUSIC Algorithm for DoA: Theory and FPGA Implementation

MUSIC Algorithm for DoA: Theory and FPGA Implementation Advanced Engineering Radar Systems

1.1K views - 3 months ago

Mastering Xilinx DMA IP cores: AXI DMA, CDMA and VDMA

Mastering Xilinx DMA IP cores: AXI DMA, CDMA and VDMA Advanced Engineering Radar Systems

1.2K views - 10 months ago

Mastering Xilinx DSP IP cores on Zynq 7000: FIR, CIC, DDS, FFT

Mastering Xilinx DSP IP cores on Zynq 7000: FIR, CIC, DDS, FFT Advanced Engineering Radar Systems

4.2K views - 1 year ago

Matched Filter: Vitis HLS Implementation

Matched Filter: Vitis HLS Implementation Advanced Engineering Radar Systems

726 views - 1 year ago

CFAR detector: Vitis HLS Implementation

CFAR detector: Vitis HLS Implementation Advanced Engineering Radar Systems

754 views - 1 year ago

Direct Digital Synthesizer: Vitis HLS implementation

Direct Digital Synthesizer: Vitis HLS implementation Advanced Engineering Radar Systems

433 views - 1 year ago

Structured Light Scanner

Structured Light Scanner Advanced Engineering Radar Systems

104 views - 1 year ago

Deep Learning with Zynq Ultrascale+ MPSoCs

Deep Learning with Zynq Ultrascale+ MPSoCs Advanced Engineering Radar Systems

1.6K views - 1 year ago

AXI DMA with Vitis HLS

AXI DMA with Vitis HLS Advanced Engineering Radar Systems

1.7K views - 2 years ago

Discrete Fourier Transform SNR derivation with modelling in Python

Discrete Fourier Transform SNR derivation with modelling in Python Advanced Engineering Radar Systems

989 views - 3 years ago

Matched Filter derivation with Python modelling

Matched Filter derivation with Python modelling Advanced Engineering Radar Systems

3.8K views - 3 years ago

How to build Embedded Linux for Zynq 7000, Zynq Ultrascale+ with Vitis 2022.1 and Buildroot

How to build Embedded Linux for Zynq 7000, Zynq Ultrascale+ with Vitis 2022.1 and Buildroot Advanced Engineering Radar Systems

12.4K views - 3 years ago

Part 1 - An overview of software optimization for ARM Cortex A9/A53

Part 1 - An overview of software optimization for ARM Cortex A9/A53 Advanced Engineering Radar Systems

1.6K views - 4 years ago

Vivado HLS: hardware acceleration for Zynq 7000 / Zynq US+. Part 3 - software vs hardware

Vivado HLS: hardware acceleration for Zynq 7000 / Zynq US+. Part 3 - software vs hardware Advanced Engineering Radar Systems

744 views - 4 years ago

Vivado HLS: hardware acceleration for Zynq 7000 / Zynq US+. Part 2 - HLS implementation

Vivado HLS: hardware acceleration for Zynq 7000 / Zynq US+. Part 2 - HLS implementation Advanced Engineering Radar Systems

1.4K views - 4 years ago

Embedded Linux for Zynq 7000 / ZU+. Boot image part2. Buildroot for Zynq 7000 / Zynq Ultrascale+

Embedded Linux for Zynq 7000 / ZU+. Boot image part2. Buildroot for Zynq 7000 / Zynq Ultrascale+ Advanced Engineering Radar Systems

1.9K views - 4 years ago

Embedded Linux for Zynq 7000 / ZU+. Boot image part 1

Embedded Linux for Zynq 7000 / ZU+. Boot image part 1 Advanced Engineering Radar Systems

4.1K views - 4 years ago

Vivado HLS: hardware acceleration for Zynq 7000 / Zynq US+. Part 1 - Introduction

Vivado HLS: hardware acceleration for Zynq 7000 / Zynq US+. Part 1 - Introduction Advanced Engineering Radar Systems

1.3K views - 4 years ago

Embedded Linux for Zynq 7000 / ZU+. Introduction

Embedded Linux for Zynq 7000 / ZU+. Introduction Advanced Engineering Radar Systems

1.7K views - 4 years ago

FPGA SoC Zynq 7000 (lesson 16): Linux for Zynq 7000, AXI GPIO example

FPGA SoC Zynq 7000 (lesson 16): Linux for Zynq 7000, AXI GPIO example Advanced Engineering Radar Systems

5K views - 5 years ago

FPGA SoC Zynq 7000 (lesson 14): Working with ADC/DAC from FMCOMMS1 module

FPGA SoC Zynq 7000 (lesson 14): Working with ADC/DAC from FMCOMMS1 module Advanced Engineering Radar Systems

3.8K views - 5 years ago

FPGA SoC Zynq 7000 (lesson 15): DSP with FMCOMMS1 and ZC706 board

FPGA SoC Zynq 7000 (lesson 15): DSP with FMCOMMS1 and ZC706 board Advanced Engineering Radar Systems

1.3K views - 5 years ago

FPGA SoC Zynq 7000 (lesson 13): AXI DMA Networking

FPGA SoC Zynq 7000 (lesson 13): AXI DMA Networking Advanced Engineering Radar Systems

3.2K views - 5 years ago

FPGA SoC Zynq 7000 (lesson 12): Lightweight IP, FSBL

FPGA SoC Zynq 7000 (lesson 12): Lightweight IP, FSBL Advanced Engineering Radar Systems

2.5K views - 5 years ago

FPGA SoC Zynq 7000 (lesson 11): AXI DMA in Scatter Gather Mode

FPGA SoC Zynq 7000 (lesson 11): AXI DMA in Scatter Gather Mode Advanced Engineering Radar Systems

3.2K views - 5 years ago

FPGA SoC Zynq 7000 (lesson 10): AXI DMA in Direct Register Mode

FPGA SoC Zynq 7000 (lesson 10): AXI DMA in Direct Register Mode Advanced Engineering Radar Systems

4.8K views - 5 years ago

Digital Signal Processing with Vivado HLS

Digital Signal Processing with Vivado HLS Advanced Engineering Radar Systems

1.7K views - 5 years ago

FPGA SoC Zynq 7000 (lesson 9): Interrupt Controller and AXI GPIOs

FPGA SoC Zynq 7000 (lesson 9): Interrupt Controller and AXI GPIOs Advanced Engineering Radar Systems

7.7K views - 5 years ago

Frequency and Phase modulation

Frequency and Phase modulation Advanced Engineering Radar Systems

677 views - 5 years ago

IQ modulator and interpolator

IQ modulator and interpolator Advanced Engineering Radar Systems

920 views - 5 years ago

Vivado HLS: Introduction

Vivado HLS: Introduction Advanced Engineering Radar Systems

1.4K views - 5 years ago

Part 3: IQ demodulator with decimation: RTL hardware design and implementation

Part 3: IQ demodulator with decimation: RTL hardware design and implementation Advanced Engineering Radar Systems

827 views - 5 years ago

Part 2: IQ demodulator with decimation: RTL hardware design and implementation

Part 2: IQ demodulator with decimation: RTL hardware design and implementation Advanced Engineering Radar Systems

970 views - 5 years ago

Part 1: IQ demodulator with decimation: RTL hardware design and implementation

Part 1: IQ demodulator with decimation: RTL hardware design and implementation Advanced Engineering Radar Systems

2.7K views - 5 years ago

FIR filter on XILINX FPGA: design with MATLAB and FPGA implementation

FIR filter on XILINX FPGA: design with MATLAB and FPGA implementation Advanced Engineering Radar Systems

5.8K views - 5 years ago

Xilinx DDS compiler IP core: sin and linear frequency modulated signal generation

Xilinx DDS compiler IP core: sin and linear frequency modulated signal generation Advanced Engineering Radar Systems

10K views - 5 years ago

3D structured light scanner prototype

3D structured light scanner prototype Advanced Engineering Radar Systems

169 views - 5 years ago