38:45 P6: 16-key matrix encoder FSM. Specifications. Drawing an example of timing diagram. Francesc J. Robert 422 views - 4 years ago
40:47 P2. Designing encoders: 10-lines to 4-bit binary encoder (Enc_10_4). Discussing specifications Francesc J. Robert 595 views - 5 years ago
36:02 P3: Inventing 2-bit adder using a hierarchical multiple-VHDL file structural design (plan C2). Francesc J. Robert 613 views - 5 years ago
31:18 UPC - EETAC - Digital Circuits and Systems (CSD) – Course presentation slides Francesc J. Robert 401 views - 5 years ago
31:20 P12: Microcontroller peripherals. TMR0 description and design equation. Timer function from FOSC/4. Francesc J. Robert 410 views - 5 years ago
27:32 P9: Microcontroller basic I/O. How to configure a PORTx pin as input or output? Francesc J. Robert 1.1K views - 5 years ago
28:41 P10: Microcontroller external interrupts to detect signal edges Francesc J. Robert 266 views - 5 years ago
42:34 P11: Microcontroller peripherals. Adding an LCD display to a serial transmitter Francesc J. Robert 611 views - 5 years ago
34:36 P10: Microcontroller adaptation of FSM. Designing a serial transmitter. Part 3: develop and test. Francesc J. Robert 307 views - 5 years ago
19:11 P10: Microcontroller adaptation of FSM. Designing a serial transmitter. Part 2: planning. Francesc J. Robert 257 views - 5 years ago
15:09 P10: Microcontroller adaptation of FSM. Designing a serial transmitter. Part 1: specifications. Francesc J. Robert 254 views - 5 years ago
47:46 P10: Microcontroller adaptation of FSM. Binary counter module 1572, plan Y, arithmetic operators Francesc J. Robert 207 views - 5 years ago
1:41:30 P10: Microcontroller adaptation of FSM. Counter BCD 1-digit using plan X on enumerating states. Francesc J. Robert 573 views - 5 years ago
27:56 P10: Microcontroller adaptation of FSM. Hardware-software diagram and basic ideas on architecture. Francesc J. Robert 463 views - 5 years ago
13:38 P9: Microcontroller basics. Using MPLABX + XC8 + Proteus VSM Francesc J. Robert 1.2K views - 5 years ago
27:11 P7: Designing a 1-digit BCD synchronous counter. Part 1: specifications. Francesc J. Robert 319 views - 5 years ago
16:02 P7: Designing a 1-digit BCD synchronous counter. Part 2 - plan Y. Francesc J. Robert 193 views - 5 years ago
21:28 P7: Designing a 1-digit BCD synchronous counter. Part 2 - plan X Francesc J. Robert 189 views - 5 years ago
33:11 P5: Designing an RS latch. Part 3 on synthesising and testing the circuit. Francesc J. Robert 328 views - 5 years ago
1:03:08 P6: Classroom luminaires system. Part 3 development, and 4-5 functional and gate-level simulation. Francesc J. Robert 570 views - 5 years ago
18:27 P5: Designing RS latch. Part 2 on plan A: deducing a circuit based on logic gates. Digital memory. Francesc J. Robert 172 views - 5 years ago
16:57 P5: Designing an RS latch. Part 1 on specifications: symbol, function table, timing diagram. Francesc J. Robert 452 views - 5 years ago
26:09 UPC - EETAC - CSD – P1. Logic gates. Driving LED from logic gates. Francesc J. Robert 361 views - 5 years ago
33:35 UPC - EETAC - CSD – P1. Logic gates. Logic margins. Noise margin high (NMH), noise margin low (NML) Francesc J. Robert 699 views - 5 years ago
15:39 UPC - EETAC - CSD – P1. Logic gates. Interfacing push-buttons and switches Francesc J. Robert 239 views - 5 years ago
34:26 P3. Designing standard circuits in VHDL using structural hierarchical multiple-file plan C2: Dec_3_8 Francesc J. Robert 522 views - 5 years ago
39:49 P2. Designing binary decoders using VHDL. Dec_3_8. Discussing specifications and equations Francesc J. Robert 396 views - 5 years ago
27:10 P3. Designing standard circuits in VHDL using structural hierarchical multiple-file (plan C2): MUX_8 Francesc J. Robert 380 views - 5 years ago
39:09 P2. Designing multiplexers using VHDL. 8-channel multiplexer, MUX_8, plan B: behavioural. Francesc J. Robert 880 views - 5 years ago
1:42:02 P2. Designing multiplexers using VHDL. Eight channel multiplexer (MUX_8). Plan A: structural (SoP) Francesc J. Robert 1.3K views - 5 years ago
10:21 P2-P3-P4. Designing combinational circuits using VHDL. Concept map Francesc J. Robert 590 views - 5 years ago
36:15 P1. Section B: Designing Circuit C using only NAND (Circuit_5) or only-NOR (Circuit_8) logic gates Francesc J. Robert 313 views - 5 years ago
1:04:05 P1. Section B: Designing Circuit C using minimised expressions: SoP (Circuit_3) and PoS (Circuit_4) Francesc J. Robert 174 views - 5 years ago
37:27 P1. Section B: Designing Circuit C using canonical maxterms (Circuit_1) and minterms (Circuit_2) Francesc J. Robert 212 views - 5 years ago
53:18 P3. Design section six: circuit adaptations for prototyping. Program a CPLD/FPGA with the Circuit_W. Francesc J. Robert 197 views - 5 years ago
1:17:48 P1. Section A: deduce the truth table of Circuit_W using VHDL EDA tools (analysis method IV) Francesc J. Robert 2.7K views - 5 years ago
33:35 P1. Section A: deduce the truth table of Circuit_W using WolframAlpha engine (analysis method IV) Francesc J. Robert 581 views - 5 years ago
37:18 P1. Section A: deduce the truth table of the Circuit_W using Proteus simulator (analysis method II) Francesc J. Robert 1.6K views - 5 years ago
38:42 P1. Section A: deduce the truth table of the Circuit_C using Boole’s algebra (analysis method III) Francesc J. Robert 461 views - 5 years ago
32:37 P1. Section A: deduce the truth table of the Circuit_K using Boole’s algebra (analysis method III) Francesc J. Robert 339 views - 5 years ago
48:34 P1. Section A: deduce the truth table of the Circuit_W using Boole’s algebra (analysis method I) Francesc J. Robert 621 views - 5 years ago
18:08 UPC - EETAC - CSD – P1. Logic gates, equations, maxterms, minterms Francesc J. Robert 516 views - 5 years ago
13:22 UPC - EETAC - CSD – P1. Section A: Analysis of a logic circuit: deduce the circuit's truth table Francesc J. Robert 727 views - 5 years ago
47:57 UPC - EETAC - CSD – P9: Microcontroller I/O. How to start a new project to develop-test-debug? Francesc J. Robert 698 views - 5 years ago
1:11:46 UPC - EETAC - CSD – P9: Microcontroller basics. I/O. Tutorial on polling inputs Francesc J. Robert 1.1K views - 5 years ago
17:38 UPC - EETAC - CSD – P8: Project J: pulse generator. Planning 3: ST button sampling and synchronising Francesc J. Robert 160 views - 5 years ago
15:15 UPC - EETAC - CSD – P6: On the design of a debouncing filter and synchroniser. Francesc J. Robert 135 views - 5 years ago
28:29 UPC - EETAC - CSD – P8: Project J: pulse generator. Planning 2: datapath + top entity Francesc J. Robert 265 views - 5 years ago
32:34 UPC - EETAC - CSD – P8: Project J: pulse generator. Planning 1 Francesc J. Robert 232 views - 5 years ago
13:29 UPC - EETAC - CSD – P5: Let’s play with an asynchronous circuit based on flip-flops Francesc J. Robert 309 views - 5 years ago
6:59 UPC - EETAC - CSD – P8: Project J: pulse generator initial draft. Francesc J. Robert 340 views - 5 years ago
35:15 UPC - EETAC - CSD – P7: Designing a 4-bit binary counter. Part 1: specifications. Francesc J. Robert 417 views - 5 years ago
2:14:58 UPC - EETAC - CSD – P6: Designing a 16-key matrix encoder FSM Francesc J. Robert 642 views - 5 years ago
1:37:40 UPC - EETAC - CSD – P5: Let’s play with an asynchronous circuit based on flip-flops Francesc J. Robert 1.1K views - 5 years ago
1:23:35 UPC - EETAC - CSD – P5: Designing a D-type flip-flop (D_FF) Francesc J. Robert 651 views - 6 years ago
29:12 UPC - EETAC - CSD - P4: Translating hierarchical schematics to VHDL (plan C2) Francesc J. Robert 615 views - 6 years ago
41:53 UPC - EETAC - CSD - P3. Designing a 1-bit adder in VHDL, structural single-file (plan A) Francesc J. Robert 475 views - 6 years ago
37:13 UPC - EETAC - CSD - P4: How fast can run this MUX_8? Francesc J. Robert 325 views - 6 years ago
1:06:57 UPC - EETAC - CSD - P4: How fast is a circuit solving arithmetic? Francesc J. Robert 902 views - 6 years ago