TechSimplified TV

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Mission : Build a Knowledge Bridge Between Academics & VLSI/Semiconductor(Si) Industry ! We provide Self Learning Free VLSI Courses for the people looking for free alternatives to proprietary and paid VLSI Courses. Use Playlist Page To Find The Complete Courses. Audience : Fresher/Graduate/Masters in Microelectronics/Electronics/VLSI. Emails : Business : [email protected] Tech Query : [email protected] Founder / Co-Editor : Mridul Sengupta [ Worked In/For VLSI Companies/Grade : Invecas (Technical Lead ), Synopsys , TexasInstruments , STMicroelectronics , InterraSystems ] Manager / Co-Editor : Munmun Dey [ Worked In/For VLSI Companies : Intel (Module Lead) , Synapse-Design , Synopsys, TexasInstruments , InterraSystems ] . Achievement Award : University Topper / Gold Medallist . Notice & Legal : www.techsimplifiedtv.in/p/terms-and-conditions.htm… Courtesy : Bensound.com , Pixabay.com, Pexels.com & Topfreeintro.com

Home Videos Live Playlists

SystemVerilog UWire Explained | Why UWire Was Introduced?

SystemVerilog UWire Explained | Why UWire Was Introduced? TechSimplified TV

13 views - 14 hours ago

OSS CAD Suite Installation | Ubuntu 24.04 & Windows 10 | Yosys, Verilator, nextpnr, GTKWave Cocotb

OSS CAD Suite Installation | Ubuntu 24.04 & Windows 10 | Yosys, Verilator, nextpnr, GTKWave Cocotb TechSimplified TV

1 day ago

N-JFET Amplifier with Self Bias | LTspice Simulation | Self-Biasing Explained

N-JFET Amplifier with Self Bias | LTspice Simulation | Self-Biasing Explained TechSimplified TV

26 views - 4 days ago

Why Packages Are Used in RTL & UVM Verification | SystemVerilog Packages Explained for Beginners

Why Packages Are Used in RTL & UVM Verification | SystemVerilog Packages Explained for Beginners TechSimplified TV

4 days ago

SystemVerilog `inside` Keyword Explained | Constraints, Assertions, Coverage & Verification Examples

SystemVerilog `inside` Keyword Explained | Constraints, Assertions, Coverage & Verification Examples TechSimplified TV

27 views - 1 week ago

What Is Testability Analysis in DFT?

What Is Testability Analysis in DFT? TechSimplified TV

37 views - 2 weeks ago

N-JFET Amplifier with Shunt Feedback | LTspice Simulation | Feedback Amplifier Explained

N-JFET Amplifier with Shunt Feedback | LTspice Simulation | Feedback Amplifier Explained TechSimplified TV

95 views - 2 weeks ago

Business Connect Podcast (BCP) | Promote Your Business to a Global Tech Audience

Business Connect Podcast (BCP) | Promote Your Business to a Global Tech Audience TechSimplified TV

60 views - 3 weeks ago

Extern in SystemVerilog Explained | Extern Tasks, Functions, Interfaces & UVM Usage | For Beginners

Extern in SystemVerilog Explained | Extern Tasks, Functions, Interfaces & UVM Usage | For Beginners TechSimplified TV

51 views - 3 weeks ago

Python Script in modification VS Code | | VLSI EDA Automation in VS Code using GitHub Copilot AI !

Python Script in modification VS Code | | VLSI EDA Automation in VS Code using GitHub Copilot AI ! TechSimplified TV

68 views - 3 weeks ago

Why $root Exists in SystemVerilog? | $root Explained with Examples, Namespaces & Verification

Why $root Exists in SystemVerilog? | $root Explained with Examples, Namespaces & Verification TechSimplified TV

19 views - 4 weeks ago

N-JFET Amplifier with Fixed Bias | LTspice Simulation | Fixed Bias JFET Amplifier Explained

N-JFET Amplifier with Fixed Bias | LTspice Simulation | Fixed Bias JFET Amplifier Explained TechSimplified TV

4 weeks ago

N-JFET Amplifier with Voltage Divider Bias | LTspice Simulation | JFET Small Signal Analysis Explain

N-JFET Amplifier with Voltage Divider Bias | LTspice Simulation | JFET Small Signal Analysis Explain TechSimplified TV

29 views - 1 month ago

Bash RegEx Automation using GitHub Copilot | Detect amd64, x86 & RPM Packages 🤖 | Shell Scripting

Bash RegEx Automation using GitHub Copilot | Detect amd64, x86 & RPM Packages 🤖 | Shell Scripting TechSimplified TV

1 month ago

🚀 SystemVerilog Pass by Reference — Explained Simply!

🚀 SystemVerilog Pass by Reference — Explained Simply! TechSimplified TV

51 views - 1 month ago

🚀 TCL Log Parsing Automation using GitHub Copilot | VS Code AI | EDA Log Analysis Tutorial

🚀 TCL Log Parsing Automation using GitHub Copilot | VS Code AI | EDA Log Analysis Tutorial TechSimplified TV

1 month ago

🚀 PERL Nested Array to Hash Conversion using GitHub Copilot | VS Code AI Coding Experiment 🤖

🚀 PERL Nested Array to Hash Conversion using GitHub Copilot | VS Code AI Coding Experiment 🤖 TechSimplified TV

1 month ago

NJFET Voltage Divider Bias Explained | LTSpice Analog Electronics Tutorial with Simulation

NJFET Voltage Divider Bias Explained | LTSpice Analog Electronics Tutorial with Simulation TechSimplified TV

75 views - 1 month ago

What is DFT in VLSI?

What is DFT in VLSI? TechSimplified TV

173 views - 1 month ago

N-JFET Amplifier Circuit Explained | Working Principle, Biasing & Small Signal Analysis

N-JFET Amplifier Circuit Explained | Working Principle, Biasing & Small Signal Analysis TechSimplified TV

44 views - 1 month ago

Physical Design Secrets: Why End Cap Cells Are Critical for Chip Reliability

Physical Design Secrets: Why End Cap Cells Are Critical for Chip Reliability TechSimplified TV

250 views - 1 month ago

Docker for VLSI & EDA Automation | Ubuntu 24.04 & Windows 10 | Python, ML & Bash 🐳

Docker for VLSI & EDA Automation | Ubuntu 24.04 & Windows 10 | Python, ML & Bash 🐳 TechSimplified TV

99 views - 1 month ago

Why Void Functions and Tasks Were Introduced in SystemVerilog | Functions vs Tasks Explained

Why Void Functions and Tasks Were Introduced in SystemVerilog | Functions vs Tasks Explained TechSimplified TV

78 views - 1 month ago

CharLib Installation on Ubuntu using Python Virtual Environment | Standard Cell Characterization

CharLib Installation on Ubuntu using Python Virtual Environment | Standard Cell Characterization TechSimplified TV

70 views - 1 month ago

SystemVerilog Randomization Explained | $random vs $urandom vs randomize() | VLSI Verification

SystemVerilog Randomization Explained | $random vs $urandom vs randomize() | VLSI Verification TechSimplified TV

45 views - 1 month ago

N-Channel JFET | Gate & Drain Characteristics Explained | LTSPICE Tutorial

N-Channel JFET | Gate & Drain Characteristics Explained | LTSPICE Tutorial TechSimplified TV

49 views - 1 month ago

Why Dynamic Type Casting & Pointers Matter in SystemVerilog

Why Dynamic Type Casting & Pointers Matter in SystemVerilog TechSimplified TV

47 views - 1 month ago

Installing Python Virtual Environments for VLSI Frontend Automation | venv Setup Only

Installing Python Virtual Environments for VLSI Frontend Automation | venv Setup Only TechSimplified TV

54 views - 1 month ago

SystemVerilog Arrays Explained: Dynamic vs Associative | Ethernet Frame & Transaction Tracking

SystemVerilog Arrays Explained: Dynamic vs Associative | Ethernet Frame & Transaction Tracking TechSimplified TV

71 views - 1 month ago

FEOL, MEOL, BEOL, Process Corners & RC Corners Explained | Complete CMOS Process & VLSI Timing Guide

FEOL, MEOL, BEOL, Process Corners & RC Corners Explained | Complete CMOS Process & VLSI Timing Guide TechSimplified TV

410 views - 1 month ago

DRC & LVS Explained in VLSI Physical Design | Mask Layout, Design Rules, NETGEN, Debugging & Flow

DRC & LVS Explained in VLSI Physical Design | Mask Layout, Design Rules, NETGEN, Debugging & Flow TechSimplified TV

629 views - 3 months ago

Variability And Timing in VLSI | RC & Process Corners, AOCV, LOCV, .lib Explained

Variability And Timing in VLSI | RC & Process Corners, AOCV, LOCV, .lib Explained TechSimplified TV

221 views - 3 months ago

Reliability and Performance in VLSI

Reliability and Performance in VLSI TechSimplified TV

169 views - 3 months ago

Static Timing Analysis | ASIC/SOC Timing, Clock Skew, Setup-Hold, Liberty, SDC, SPEF, SDF, OpenTimer

Static Timing Analysis | ASIC/SOC Timing, Clock Skew, Setup-Hold, Liberty, SDC, SPEF, SDF, OpenTimer TechSimplified TV

610 views - 3 months ago

All About Interconnect in VLSI : A Complete Guide

All About Interconnect in VLSI : A Complete Guide TechSimplified TV

282 views - 3 months ago

Shell Scripting Marathon (Beginner to Advanced) | BASH Basics, SED, AWK, Loops & Automation

Shell Scripting Marathon (Beginner to Advanced) | BASH Basics, SED, AWK, Loops & Automation TechSimplified TV

352 views - 4 months ago

Physical Design in VLSI : The Complete Guide Marathon

Physical Design in VLSI : The Complete Guide Marathon TechSimplified TV

1K views - 4 months ago

Find VLSI Internships & Jobs | LinkedIn & Glassdoor Secrets for Freshers | VLSI Salary Growth Guide

Find VLSI Internships & Jobs | LinkedIn & Glassdoor Secrets for Freshers | VLSI Salary Growth Guide TechSimplified TV

218 views - 4 months ago

SPICE Marathon: Complete Guide to Circuit Analysis with NGSPICE & GNU-PLOT | From Basics to Advanced

SPICE Marathon: Complete Guide to Circuit Analysis with NGSPICE & GNU-PLOT | From Basics to Advanced TechSimplified TV

263 views - 4 months ago

Power Aware VLSI Designs | PMU, Power Domains, UPF & Special Cells | Power, Performance & Area

Power Aware VLSI Designs | PMU, Power Domains, UPF & Special Cells | Power, Performance & Area TechSimplified TV

936 views - 5 months ago

💡 Master VLSI Ecosystem in One Video | Complete VLSI Design Domains Explained !

💡 Master VLSI Ecosystem in One Video | Complete VLSI Design Domains Explained ! TechSimplified TV

411 views - 5 months ago

SystemVerilog Dynamic Memory Allocation Explained | Arrays, Queues, Associative Arrays & Testbench

SystemVerilog Dynamic Memory Allocation Explained | Arrays, Queues, Associative Arrays & Testbench TechSimplified TV

74 views - 5 months ago

SystemVerilog fork...join vs fork...join_any vs fork...join_none | Examples & Use Cases Explained

SystemVerilog fork...join vs fork...join_any vs fork...join_none | Examples & Use Cases Explained TechSimplified TV

87 views - 5 months ago

Why SystemVerilog Borrowed These 5 Powerful Concepts from Programming Languages ?

Why SystemVerilog Borrowed These 5 Powerful Concepts from Programming Languages ? TechSimplified TV

122 views - 6 months ago

Mastering Interfaces in SystemVerilog: From Basics to Modports!

Mastering Interfaces in SystemVerilog: From Basics to Modports! TechSimplified TV

276 views - 6 months ago

Clock & Delay in VLSI – Complete Marathon

Clock & Delay in VLSI – Complete Marathon TechSimplified TV

511 views - 6 months ago

LTSpice(v24) Bridge Rectifier Circuit Explained | Full-Wave Rectification | Transient Analysis !

LTSpice(v24) Bridge Rectifier Circuit Explained | Full-Wave Rectification | Transient Analysis ! TechSimplified TV

638 views - 6 months ago

LTSpice(v24) Exploring Diode & Pasive Elements | Frequency & Transient Response Circuits Explained !

LTSpice(v24) Exploring Diode & Pasive Elements | Frequency & Transient Response Circuits Explained ! TechSimplified TV

422 views - 6 months ago

LTSpice(v24) Exploring Diode Waveform Shaping Circuit : DC Sources | DC Analysis

LTSpice(v24) Exploring Diode Waveform Shaping Circuit : DC Sources | DC Analysis TechSimplified TV

100 views - 7 months ago

CMOS & TTL Logic Gate Simulation Using LTSpice(v24) | AND, OR, NOT, NAND, NOR, XOR, XNOR | Marathon

CMOS & TTL Logic Gate Simulation Using LTSpice(v24) | AND, OR, NOT, NAND, NOR, XOR, XNOR | Marathon TechSimplified TV

846 views - 7 months ago

LCR Parallel CKT Config 2 Transient And AC Analysis SPICE EP 34

LCR Parallel CKT Config 2 Transient And AC Analysis SPICE EP 34 TechSimplified TV

76 views - 7 months ago

What is Testing in VLSI ?

What is Testing in VLSI ? TechSimplified TV

421 views - 7 months ago

Defect & Fault Modelling in VLSI

Defect & Fault Modelling in VLSI TechSimplified TV

303 views - 8 months ago

Linux For VLSI Marathon | For ALL VLSI Aspirants

Linux For VLSI Marathon | For ALL VLSI Aspirants TechSimplified TV

919 views - 8 months ago

LTSpice(v24) Exploring R-L-C Parallel Circuit : PWL & AC Sources | Transient & AC Analysis

LTSpice(v24) Exploring R-L-C Parallel Circuit : PWL & AC Sources | Transient & AC Analysis TechSimplified TV

149 views - 8 months ago

LTSpice(v24) - RC Ladder Circuit Made Simple | Transient Response to Sine Wave Input

LTSpice(v24) - RC Ladder Circuit Made Simple | Transient Response to Sine Wave Input TechSimplified TV

224 views - 8 months ago

Why SystemVerilog Introduced bit and logic Over reg and wire | Upgrade Explained

Why SystemVerilog Introduced bit and logic Over reg and wire | Upgrade Explained TechSimplified TV

163 views - 8 months ago

VLSI Physical Design Verification Deep Dive : The Complete Marathon

VLSI Physical Design Verification Deep Dive : The Complete Marathon TechSimplified TV

3.2K views - 9 months ago

LTSpice (v24): TTL NOR Gate Simulation | Response by Transient Analysis

LTSpice (v24): TTL NOR Gate Simulation | Response by Transient Analysis TechSimplified TV

256 views - 9 months ago

LTSpice (v24): TTL NAND Gate Simulation | Response by Transient Analysis

LTSpice (v24): TTL NAND Gate Simulation | Response by Transient Analysis TechSimplified TV

465 views - 9 months ago