BitLemon

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Educational videos about computer science and computer architecture.

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Why 10GHz Silicon CPUs Are Impossible (Probably)

Why 10GHz Silicon CPUs Are Impossible (Probably) BitLemon

365.6K views - 1 month ago

Out-of-Order Execution (Tomasulo's Algorithm)

Out-of-Order Execution (Tomasulo's Algorithm) BitLemon

20.9K views - 3 months ago

CPU Architecture Explained

CPU Architecture Explained BitLemon

120.2K views - 5 months ago

How Interrupts Work in Modern Computers

How Interrupts Work in Modern Computers BitLemon

45.9K views - 8 months ago

Why Programs Use Stack, Heap, and Other Memory Segments

Why Programs Use Stack, Heap, and Other Memory Segments BitLemon

35.7K views - 9 months ago

What is a Page Fault

What is a Page Fault BitLemon

9.5K views - 10 months ago

Cache Simulator in C++: Measuring Cache Hit Rate

Cache Simulator in C++: Measuring Cache Hit Rate BitLemon

3.9K views - 11 months ago

Cache Simulator in C++: Building a Basic Framework

Cache Simulator in C++: Building a Basic Framework BitLemon

5.4K views - 11 months ago

MultiLevel Page Tables: How Virtual Memory is Optimized (Animation)

MultiLevel Page Tables: How Virtual Memory is Optimized (Animation) BitLemon

17.2K views - 11 months ago

Memory Mapped IO vs Port Mapped IO (Animation)

Memory Mapped IO vs Port Mapped IO (Animation) BitLemon

27.5K views - 1 year ago

DMA Controller: How Peripheral Devices Transfer Data to RAM

DMA Controller: How Peripheral Devices Transfer Data to RAM BitLemon

31.1K views - 1 year ago

Page Tables and MMU: How Virtual Memory Actually Works Behind the Scenes (Animation)

Page Tables and MMU: How Virtual Memory Actually Works Behind the Scenes (Animation) BitLemon

57.6K views - 1 year ago

Virtual Memory Explained (including Paging)

Virtual Memory Explained (including Paging) BitLemon

113.8K views - 1 year ago

SRAM vs DRAM: The Speed Difference between Cache and RAM (Animation)

SRAM vs DRAM: The Speed Difference between Cache and RAM (Animation) BitLemon

14.3K views - 1 year ago

Cache Hierarchy: How Modern CPU Caches Are Organized (L1, L2 and L3)

Cache Hierarchy: How Modern CPU Caches Are Organized (L1, L2 and L3) BitLemon

27.4K views - 1 year ago

CPU Cache Write Policies (Write Through, Write Back, Write Allocate, No Write Allocate)

CPU Cache Write Policies (Write Through, Write Back, Write Allocate, No Write Allocate) BitLemon

15.3K views - 1 year ago

Cache Replacement Policies (LRU, Tree-pLRU, MRU, QLRU, FIFO, LFU, Random and more)

Cache Replacement Policies (LRU, Tree-pLRU, MRU, QLRU, FIFO, LFU, Random and more) BitLemon

17K views - 1 year ago

How Cache Works Inside a CPU

How Cache Works Inside a CPU BitLemon

100.7K views - 1 year ago

1 Thread vs. 1000 Threads: How Fast Can C++ Increment a Value?

1 Thread vs. 1000 Threads: How Fast Can C++ Increment a Value? BitLemon

1.6K views - 1 year ago

Bitwise Operations: The Most Underappreciated Feature in Low-Level Programming

Bitwise Operations: The Most Underappreciated Feature in Low-Level Programming BitLemon

1.7K views - 1 year ago

C++ Vectors Explained in 168 seconds

C++ Vectors Explained in 168 seconds BitLemon

7.6K views - 1 year ago