Chip Design with Rashid

@UCkZyWD6gVPsfJIM8h3Dy4Rw - 10.9K subscribers

Welcome to Chip Design with Rashid! This channel is your ultimate resource for mastering Digital IC Design, whether you're a student just starting or a seasoned professional looking to sharpen your skills. I'm Rashid, an industry veteran with over 24 years of experience in Digital IC Design. My career includes: 18 years at Intel, where I grew from an Engineer to a Manager. A subsequent role at Cadence. Now based in Colorado, USA, I hold degrees in Electronics Engineering and bring a truly international perspective to my teaching, having worked globally in Pakistan, Sweden, Germany, and Ireland. I've created hundreds of free videos, and I know it can be challenging to navigate them all. To make your learning journey easier, I've organized a complete curriculum on my website: www.chipdesignrashid.github.io/chip-design-website While the vast majority of my content is free, the best way to benefit from the channel is to join my membership. USA: $2.99/month India: ₹89/month

Home Videos Live Playlists

ASIC Synthesis, video 2, Pre-reqs, Taking O’Soc1 (cpu core and cpu top) through the flow

ASIC Synthesis, video 2, Pre-reqs, Taking O’Soc1 (cpu core and cpu top) through the flow Chip Design with Rashid

89 views - 2 days ago

ASIC Synthesis Video 1 Introduction - Where Synthesis flow fits in the Design Flow

ASIC Synthesis Video 1 Introduction - Where Synthesis flow fits in the Design Flow Chip Design with Rashid

119 views - 3 days ago

SSTA Video 23, Modeling Asymmetric Delay distributions with 3 Moments, How to Model OCV on Wires

SSTA Video 23, Modeling Asymmetric Delay distributions with 3 Moments, How to Model OCV on Wires Chip Design with Rashid

5 days ago

SSTA Video 22, Modeling POCV/SOCVM with LUT based Sigma, Why Asymmetric Distribution

SSTA Video 22, Modeling POCV/SOCVM with LUT based Sigma, Why Asymmetric Distribution Chip Design with Rashid

97 views - 1 week ago

RISCV CPU in system Verilog Video 26 - Memory Wrapper structure and CPU TOP verification

RISCV CPU in system Verilog Video 26 - Memory Wrapper structure and CPU TOP verification Chip Design with Rashid

1 week ago

SSTA Video 21, POCV/SOCV Approach with Coefficients & LVF

SSTA Video 21, POCV/SOCV Approach with Coefficients & LVF Chip Design with Rashid

2 weeks ago

RISCV-CPU in System Verilog Video 25 - Building CPU CORE and CPU TOP, Separating Memories; why?

RISCV-CPU in System Verilog Video 25 - Building CPU CORE and CPU TOP, Separating Memories; why? Chip Design with Rashid

2 weeks ago

SSTA Video 20, Details of Fixed Derating & AOCVM - Distance & Stage based derating

SSTA Video 20, Details of Fixed Derating & AOCVM - Distance & Stage based derating Chip Design with Rashid

2 weeks ago

RISCV-CPU in System Verilog, Video 24, Register File Implementation

RISCV-CPU in System Verilog, Video 24, Register File Implementation Chip Design with Rashid

275 views - 3 weeks ago

SSTA Video 19, Modeling OCV in the STA - Overview of Different Techniques

SSTA Video 19, Modeling OCV in the STA - Overview of Different Techniques Chip Design with Rashid

3 weeks ago

RISCV-CPU in System Verilog, Video 23, Program Counter (PC) Implementation

RISCV-CPU in System Verilog, Video 23, Program Counter (PC) Implementation Chip Design with Rashid

3 weeks ago

SSTA Video 18, How Modern Timing Tools Simplify SSTA Math

SSTA Video 18, How Modern Timing Tools Simplify SSTA Math Chip Design with Rashid

4 weeks ago

RISCV-CPU in System Verilog, Video 22, Controller Module Implementation

RISCV-CPU in System Verilog, Video 22, Controller Module Implementation Chip Design with Rashid

151 views - 4 weeks ago

RISCV-CPU in System Verilog, video 21, Branch Control Unit Design & Verification

RISCV-CPU in System Verilog, video 21, Branch Control Unit Design & Verification Chip Design with Rashid

1 month ago

SSTA, Video 17, Max Operation, Fully correlated vs Independent

SSTA, Video 17, Max Operation, Fully correlated vs Independent Chip Design with Rashid

1 month ago

RISC-V CPU in System Verilog - Video 20, Load Alignment Unit (LAU) Design & Verification

RISC-V CPU in System Verilog - Video 20, Load Alignment Unit (LAU) Design & Verification Chip Design with Rashid

1 month ago

RISCV CPU in System Verilog - Video 19, Building a Store Alignment Unit (SAU), RTL Walk through

RISCV CPU in System Verilog - Video 19, Building a Store Alignment Unit (SAU), RTL Walk through Chip Design with Rashid

1 month ago

SSTA Video 16, Sum Operation: Fully Correlated vs. Independent Variation

SSTA Video 16, Sum Operation: Fully Correlated vs. Independent Variation Chip Design with Rashid

1 month ago

RISCV CPU in System Verilog ,video 18, Instruction decoder + Immediate extractor SV code walkthrough

RISCV CPU in System Verilog ,video 18, Instruction decoder + Immediate extractor SV code walkthrough Chip Design with Rashid

1 month ago

SSTA Video 15, Relative spread of a timing path where cell delay variations are correlated

SSTA Video 15, Relative spread of a timing path where cell delay variations are correlated Chip Design with Rashid

215 views - 1 month ago

RISCV CPU in System Verilog, Video 17, 10 Essential System Verilog Constructs Explained

RISCV CPU in System Verilog, Video 17, 10 Essential System Verilog Constructs Explained Chip Design with Rashid

1 month ago

SSTA Video 14, Timing Path Variance with Correlation Explained

SSTA Video 14, Timing Path Variance with Correlation Explained Chip Design with Rashid

1 month ago

RISCV CPU in SV: Video #16, Shifts, Logical Instructions, and Full ALU Datapath in System Verilog

RISCV CPU in SV: Video #16, Shifts, Logical Instructions, and Full ALU Datapath in System Verilog Chip Design with Rashid

1 month ago

SSTA Video #13, The SSTA Averaging Effect: 1/√n Derivation

SSTA Video #13, The SSTA Averaging Effect: 1/√n Derivation Chip Design with Rashid

1 month ago

RISCV CPU in System verilog, Video #15, Implementing Set Less Than SLT & SLTU Instructions

RISCV CPU in System verilog, Video #15, Implementing Set Less Than SLT & SLTU Instructions Chip Design with Rashid

1 month ago

SSTA video #: 12 Systematic vs Random Process Variations [Die-to-Die & Within-Die]

SSTA video #: 12 Systematic vs Random Process Variations [Die-to-Die & Within-Die] Chip Design with Rashid

259 views - 1 month ago

Exciting Update: New STA Foundation Books & Upcoming Course!

Exciting Update: New STA Foundation Books & Upcoming Course! Chip Design with Rashid

268 views - 1 month ago

RISCV CPU design in SV, Video 14, ALU Flags Part 3: Subtraction Overflow & SystemVerilog Walkthrough

RISCV CPU design in SV, Video 14, ALU Flags Part 3: Subtraction Overflow & SystemVerilog Walkthrough Chip Design with Rashid

115 views - 1 month ago

RISCV CPU in System Verilog Video 13- ALU Flags Part 2: Subtraction Carry & Inverted Borrow Logic

RISCV CPU in System Verilog Video 13- ALU Flags Part 2: Subtraction Carry & Inverted Borrow Logic Chip Design with Rashid

1 month ago

Statistical Timing: Video 11, Process to Delay: The 4 Stages of SSTA Variation

Statistical Timing: Video 11, Process to Delay: The 4 Stages of SSTA Variation Chip Design with Rashid

2 months ago

RISCV CPU in System Verilog, Video 12, ALU Flags Part 1: Carry vs. Overflow in Addition

RISCV CPU in System Verilog, Video 12, ALU Flags Part 1: Carry vs. Overflow in Addition Chip Design with Rashid

101 views - 2 months ago

RISCV CPU in system verilog, video 11, Adders & Subtractors: Behavioral vs. Low-Level RTL

RISCV CPU in system verilog, video 11, Adders & Subtractors: Behavioral vs. Low-Level RTL Chip Design with Rashid

2 months ago

Advanced STA, video 10, Deterministic vs. Statistical STA: When to Use Which

Advanced STA, video 10, Deterministic vs. Statistical STA: When to Use Which Chip Design with Rashid

2 months ago

RISCV CPU in System Verilog, Video 10, ALU part 2 - Unsigned to Signed conversion in Python

RISCV CPU in System Verilog, Video 10, ALU part 2 - Unsigned to Signed conversion in Python Chip Design with Rashid

2 months ago

RISCV CPU in System Verilog, Video 9, ALU Implementation - overview

RISCV CPU in System Verilog, Video 9, ALU Implementation - overview Chip Design with Rashid

328 views - 2 months ago

Advanced STA, video 9, Benefits of traditional STA & need for SSTA

Advanced STA, video 9, Benefits of traditional STA & need for SSTA Chip Design with Rashid

2 months ago

RISCV CPU in System Verilog, Video 8, ALU Muxes, Packages, Ternary assign, & Cocotb Verification

RISCV CPU in System Verilog, Video 8, ALU Muxes, Packages, Ternary assign, & Cocotb Verification Chip Design with Rashid

192 views - 2 months ago

Advanced STA, video 8, Building Intuition of OCV: Fabrication (Oxidation to Lithography)

Advanced STA, video 8, Building Intuition of OCV: Fabrication (Oxidation to Lithography) Chip Design with Rashid

2 months ago

RISCV CPU Design in System Verilog, Video 7, Use of if-else, assign, unique case, parameters, & enum

RISCV CPU Design in System Verilog, Video 7, Use of if-else, assign, unique case, parameters, & enum Chip Design with Rashid

2 months ago

Advanced STA, video 7, On Die Variations / On Chip Variations (Intro)

Advanced STA, video 7, On Die Variations / On Chip Variations (Intro) Chip Design with Rashid

374 views - 2 months ago

RISCV CPU Design in System Verilog, Video 6, Verification of RF WB MUX with Icarus and cocotb python

RISCV CPU Design in System Verilog, Video 6, Verification of RF WB MUX with Icarus and cocotb python Chip Design with Rashid

2 months ago

Advanced STA - video 6 - How Temperature Impacts Transistors vs. Interconnects

Advanced STA - video 6 - How Temperature Impacts Transistors vs. Interconnects Chip Design with Rashid

3 months ago

CPU Design in System Verilog Video 5 Coding Our First CPU Module: The SystemVerilog Write-Back Mux

CPU Design in System Verilog Video 5 Coding Our First CPU Module: The SystemVerilog Write-Back Mux Chip Design with Rashid

619 views - 3 months ago

Advanced STA, Video 5, Inductive Voltage Droop and PDN Protection

Advanced STA, Video 5, Inductive Voltage Droop and PDN Protection Chip Design with Rashid

3 months ago

RISCV CPU Design in System Verilog, Video 4: Automating Simulation with Python & Cocotb (on NAND2)

RISCV CPU Design in System Verilog, Video 4: Automating Simulation with Python & Cocotb (on NAND2) Chip Design with Rashid

423 views - 3 months ago

Advanced STA - Video 4 - Power Supply variations - Static IR drop

Advanced STA - Video 4 - Power Supply variations - Static IR drop Chip Design with Rashid

563 views - 3 months ago

RISC-V CPU Design in System Verilog, Video 3, First RTL Simulation: NAND Gate & GTKWave

RISC-V CPU Design in System Verilog, Video 3, First RTL Simulation: NAND Gate & GTKWave Chip Design with Rashid

392 views - 3 months ago

RISCV CPU Design in System verilog, video 2, The Silicon Mindset & Icarus Setup

RISCV CPU Design in System verilog, video 2, The Silicon Mindset & Icarus Setup Chip Design with Rashid

524 views - 3 months ago

Advanced STA, Video 3, Process Control Monitoring during Wafer Sort

Advanced STA, Video 3, Process Control Monitoring during Wafer Sort Chip Design with Rashid

3 months ago

RISCV CPU Design in System verilog, video 1, Series Overview & The RTL Blueprint

RISCV CPU Design in System verilog, video 1, Series Overview & The RTL Blueprint Chip Design with Rashid

1.4K views - 3 months ago

Advanced STA, Video 2, Silicon Profiling, Yield, and Binning

Advanced STA, Video 2, Silicon Profiling, Yield, and Binning Chip Design with Rashid

3 months ago

RISCV CPU Design in python - Video 15- Microarchitecture verification is DONE!!

RISCV CPU Design in python - Video 15- Microarchitecture verification is DONE!! Chip Design with Rashid

264 views - 3 months ago

Advanced STA, Video 1, Understanding PVT and Global Corners

Advanced STA, Video 1, Understanding PVT and Global Corners Chip Design with Rashid

3 months ago

RISCV-CPU Design in Python - Video 14, New Partitions & Automated Top level Verification

RISCV-CPU Design in Python - Video 14, New Partitions & Automated Top level Verification Chip Design with Rashid

210 views - 3 months ago

RISCV CPU Design in Python - Video 13- Top level Python Code

RISCV CPU Design in Python - Video 13- Top level Python Code Chip Design with Rashid

151 views - 3 months ago

Timing Constraints - video 29 - Wrap up of Timing Constraints and whats next

Timing Constraints - video 29 - Wrap up of Timing Constraints and whats next Chip Design with Rashid

4 months ago

RISCV CPU Design in Python - Video 12 - CPU Controller

RISCV CPU Design in Python - Video 12 - CPU Controller Chip Design with Rashid

142 views - 4 months ago

RISCV CPU in Python - Video 11 - Data Path Python Code review

RISCV CPU in Python - Video 11 - Data Path Python Code review Chip Design with Rashid

179 views - 4 months ago

RISCV-CPU in Python, Video 10, Putting it all together - entire CPU in Python

RISCV-CPU in Python, Video 10, Putting it all together - entire CPU in Python Chip Design with Rashid

118 views - 4 months ago

Timing Constraints - Video 28 - Input Path Analysis Part 1

Timing Constraints - Video 28 - Input Path Analysis Part 1 Chip Design with Rashid

4 months ago