Explore VLSI

@UCnnhD-6aZ6yo2vkrLyWWj9w - 10.5K subscribers

👉 E X P L O R E V L S I - Powered by LOGIC CELLS TECHNOLOGIES Hi Everyone! 👋 Welcome to VLSI world. I'm Sujay working in VLSI Industry sharing my knowledge through "Explore VLSI". Aim is to share/discuss some advanced concepts of Electronics which really help in building careers in Electronics core domains like VLSI IC Design and Verification, Embedded System etc. for Young budding engineers. It helps to understand the concept better and for preparation for job Interviews. Visit 🎞️ youtube.com/@ExploreElectronics which covers the Basics of Electronics. visit 💛♥️ youtube.com/@ExploreElectronicsKannada which covers Basics of Electronics in Kannada This Channel helps to get into 👉VLSI Jobs 👉RTL Design Engineer 👉Design Verification Engineer 🎯 Target Core Domain Jobs 🎯 SUBSCRIBE TO THE CHANNEL FOR VIDEO UPDATES

Home Videos Live Playlists

Day 75 Virtual sequence, Virtual sequencer

Day 75 Virtual sequence, Virtual sequencer Explore VLSI

94 views - 3 days ago

Day 74 Sequences and types of Sequences #100daysofdv

Day 74 Sequences and types of Sequences #100daysofdv Explore VLSI

1 week ago

Day 73 UVM Sequencer and Arbitration of Sequences #100daysofdv

Day 73 UVM Sequencer and Arbitration of Sequences #100daysofdv Explore VLSI

1 month ago

Day 72 UVM Sequence Body Method Types - 3 Ways

Day 72 UVM Sequence Body Method Types - 3 Ways Explore VLSI

335 views - 1 month ago

Day 71 UVM Sequence Sequencer Driver Handshake Explained #100daysofdv

Day 71 UVM Sequence Sequencer Driver Handshake Explained #100daysofdv Explore VLSI

1 month ago

Day 70 UVM Run Phase & Objections Explained #100daysofdv

Day 70 UVM Run Phase & Objections Explained #100daysofdv Explore VLSI

1 month ago

Day 69 UVM Connect Phase | TLM Ports Explained #100daysofdv

Day 69 UVM Connect Phase | TLM Ports Explained #100daysofdv Explore VLSI

1 month ago

Day 68 UVM Field Macros Explained | #100daysofdv

Day 68 UVM Field Macros Explained | #100daysofdv Explore VLSI

1 month ago

Day 67 UVM Config DB Deep Dive | Virtual Interface Passing & Instance Path | #100daysofdv

Day 67 UVM Config DB Deep Dive | Virtual Interface Passing & Instance Path | #100daysofdv Explore VLSI

1 month ago

Day 66 UVM Build Phase Explained in Detail | Component Creation & Config DB | #100daysofdv

Day 66 UVM Build Phase Explained in Detail | Component Creation & Config DB | #100daysofdv Explore VLSI

1 month ago

Day 65 UVM phases Explained with code and logs | #100daysofdv

Day 65 UVM phases Explained with code and logs | #100daysofdv Explore VLSI

695 views - 1 month ago

Day 64 UVM Phases Explained | Top-Down vs Bottom-Up | #100daysofdv

Day 64 UVM Phases Explained | Top-Down vs Bottom-Up | #100daysofdv Explore VLSI

1 month ago

Day 63 UVM Factory Explained | Registration, create() & Factory Override #100daysofdv

Day 63 UVM Factory Explained | Registration, create() & Factory Override #100daysofdv Explore VLSI

1 month ago

Day 62 UVM Print Macros, Verbosity Levels Explained | Print Smart Logs | 100 days of DV

Day 62 UVM Print Macros, Verbosity Levels Explained | Print Smart Logs | 100 days of DV Explore VLSI

3 months ago

Day 61 UVM Internals Explained: Start with Macros vs Package | 100 days of dv

Day 61 UVM Internals Explained: Start with Macros vs Package | 100 days of dv Explore VLSI

867 views - 3 months ago

Day 60 Part 2 Scoreboard class in System Verilog Testbench | 100 days of dv

Day 60 Part 2 Scoreboard class in System Verilog Testbench | 100 days of dv Explore VLSI

3 months ago

Day 60 Driver, Monitor class in System Verilog Testbench | 100 days of dv

Day 60 Driver, Monitor class in System Verilog Testbench | 100 days of dv Explore VLSI

3 months ago

Day 59 Transaction, Generator class in System Verilog Testbench | 100 days of dv

Day 59 Transaction, Generator class in System Verilog Testbench | 100 days of dv Explore VLSI

3 months ago

Day 58 SystemVerilog Environment Class from Scratch | Systemverilog Verification Testbench

Day 58 SystemVerilog Environment Class from Scratch | Systemverilog Verification Testbench Explore VLSI

3 months ago

Day 57 Program block in System Verilog | System Verilog Program Test | Design Verification

Day 57 Program block in System Verilog | System Verilog Program Test | Design Verification Explore VLSI

4 months ago

Day 56 System Verilog Interface, Clocking Block, Modport Explained | Design Verification

Day 56 System Verilog Interface, Clocking Block, Modport Explained | Design Verification Explore VLSI

1.5K views - 4 months ago

Day 55 System Verilog Testbench | Components and How they communicate

Day 55 System Verilog Testbench | Components and How they communicate Explore VLSI

1.2K views - 4 months ago

Day 54 Scheduling Semantics in System Verilog | Event Queue in SV

Day 54 Scheduling Semantics in System Verilog | Event Queue in SV Explore VLSI

4 months ago

Day 53 mailbox in sv | Mailbox types, Common use cases and example codes

Day 53 mailbox in sv | Mailbox types, Common use cases and example codes Explore VLSI

4 months ago

Day 52 Semaphore in systemverilog with use cases & example codes.

Day 52 Semaphore in systemverilog with use cases & example codes. Explore VLSI

4 months ago

Day 51 Events in systemverilog | wait for event | synchronization

Day 51 Events in systemverilog | wait for event | synchronization Explore VLSI

4 months ago

Day 50 SV Constraints use cases & Interview Questions

Day 50 SV Constraints use cases & Interview Questions Explore VLSI

4 months ago

Day 49 Constraints in System verilog (part 2) | Types | Common Mistakes

Day 49 Constraints in System verilog (part 2) | Types | Common Mistakes Explore VLSI

4 months ago

Day 48 Constraints in System verilog | Types | Common Mistakes

Day 48 Constraints in System verilog | Types | Common Mistakes Explore VLSI

5 months ago

day 47 Randomization, constraints in System verilog

day 47 Randomization, constraints in System verilog Explore VLSI

910 views - 5 months ago

day 46 abstract class, scope resolution operator in System verilog

day 46 abstract class, scope resolution operator in System verilog Explore VLSI

5 months ago

Day 45 Copy Methods in SystemVerilog Explained | Shallow Copy, Deep Copy | #100daysofdv

Day 45 Copy Methods in SystemVerilog Explained | Shallow Copy, Deep Copy | #100daysofdv Explore VLSI

1K views - 5 months ago

Day 44 SystemVerilog Polymorphism Explained | Virtual Keyword | #100daysofdv

Day 44 SystemVerilog Polymorphism Explained | Virtual Keyword | #100daysofdv Explore VLSI

5 months ago

How Integrated Circuits Are Made (IC Chips Explained) | The Sand-to-Silicon Process

E

How Integrated Circuits Are Made (IC Chips Explained) | The Sand-to-Silicon Process Explore VLSI and Explore Electronics

1.8K views - 5 months ago

Day 43 SystemVerilog super keyword Explained | #100daysofdv

Day 43 SystemVerilog super keyword Explained | #100daysofdv Explore VLSI

5 months ago

Day 42 SystemVerilog inheritance, super keyword Explained | #100daysofdv

Day 42 SystemVerilog inheritance, super keyword Explained | #100daysofdv Explore VLSI

5 months ago

Day 41 SystemVerilog this keyword Explained | #100daysofdv

Day 41 SystemVerilog this keyword Explained | #100daysofdv Explore VLSI

5 months ago

Day 40 SystemVerilog Class Explained | Object Creation, new() Constructor #100daysofdv

Day 40 SystemVerilog Class Explained | Object Creation, new() Constructor #100daysofdv Explore VLSI

850 views - 6 months ago

Day 39 SystemVerilog Queue Explained | Concept, Methods, Real Use Case | System Verilog #100daysofdv

Day 39 SystemVerilog Queue Explained | Concept, Methods, Real Use Case | System Verilog #100daysofdv Explore VLSI

6 months ago

Day 38 System Verilog Associative Arrays Explained with Examples | System Verilog #100daysofdv

Day 38 System Verilog Associative Arrays Explained with Examples | System Verilog #100daysofdv Explore VLSI

6 months ago

Day 37 System Verilog Dynamic Arrays Explained with Examples | System Verilog Tutorial #100daysofdv

Day 37 System Verilog Dynamic Arrays Explained with Examples | System Verilog Tutorial #100daysofdv Explore VLSI

6 months ago

Day 36 Arrays in System Verilog | Packed, unpacked, multidimensional arrays | 100 days of DV #vlsi

Day 36 Arrays in System Verilog | Packed, unpacked, multidimensional arrays | 100 days of DV #vlsi Explore VLSI

6 months ago

Xilinx Vivado 2025 simulation tutorial | Step by step procedure | Vivado Tutorial for RTL Design

Xilinx Vivado 2025 simulation tutorial | Step by step procedure | Vivado Tutorial for RTL Design Explore VLSI

7.1K views - 6 months ago

Day 35 fork join and types in System Verilog | 100 days of design verification

Day 35 fork join and types in System Verilog | 100 days of design verification Explore VLSI

6 months ago

Day 34 Data types in System Verilog | 100 days of design verification

Day 34 Data types in System Verilog | 100 days of design verification Explore VLSI

6 months ago

Day 33 SystemVerilog always_comb, always_ff, always_latch Explained | Difference from Verilog always

Day 33 SystemVerilog always_comb, always_ff, always_latch Explained | Difference from Verilog always Explore VLSI

6 months ago

Day 32 System Verilog Enum Data Type Explained with Examples and Use Cases

Day 32 System Verilog Enum Data Type Explained with Examples and Use Cases Explore VLSI

6 months ago

Day 31 Why System Verilog | Data types | verilog vs system verilog | 100 days of design verification

Day 31 Why System Verilog | Data types | verilog vs system verilog | 100 days of design verification Explore VLSI

1K views - 6 months ago

Day 30 Verilog Event Queue Explained | Simulation Regions & Scheduling Semantics in Verilog HDL

Day 30 Verilog Event Queue Explained | Simulation Regions & Scheduling Semantics in Verilog HDL Explore VLSI

6 months ago

Day 29 Verilog User Defined Primitives (UDP) | Sequential, Combinational UDP Explained with Examples

Day 29 Verilog User Defined Primitives (UDP) | Sequential, Combinational UDP Explained with Examples Explore VLSI

6 months ago

Day 28 Verilog Generate Block Explained | if-generate, for-generate, case-generate with Examples

Day 28 Verilog Generate Block Explained | if-generate, for-generate, case-generate with Examples Explore VLSI

6 months ago

Day 27 Verilog File Read write operations Explained with examples

Day 27 Verilog File Read write operations Explained with examples Explore VLSI

7 months ago

Day 26 RAM and ROM Design in Verilog | Memory Design Explained with Testbenches

Day 26 RAM and ROM Design in Verilog | Memory Design Explained with Testbenches Explore VLSI

7 months ago

Day 25 – Design and verification of RAM Memory | Use of $clog2 in Memory Design #100daysofDV

Day 25 – Design and verification of RAM Memory | Use of $clog2 in Memory Design #100daysofDV Explore VLSI

1.2K views - 7 months ago

Day 24 – Use cases of Compiler Directives in Verilog design and testbench codes #100daysofDV

Day 24 – Use cases of Compiler Directives in Verilog design and testbench codes #100daysofDV Explore VLSI

7 months ago

Day 23 – Compiler Directives in Verilog | Verilog Preprocessor Directives #100daysofDV

Day 23 – Compiler Directives in Verilog | Verilog Preprocessor Directives #100daysofDV Explore VLSI

7 months ago

Day 21 - 🚀 Functions in verilog #100daysofDV #functions

Day 21 - 🚀 Functions in verilog #100daysofDV #functions Explore VLSI

7 months ago

Day 22 - 🚀 Tasks in verilog, Types, Task vs Functions Differences #100daysofDV #functions #tasks

Day 22 - 🚀 Tasks in verilog, Types, Task vs Functions Differences #100daysofDV #functions #tasks Explore VLSI

7 months ago

Day 20 - 🚀 Clock Generation Methods #100daysofDV #fsm

Day 20 - 🚀 Clock Generation Methods #100daysofDV #fsm Explore VLSI

7 months ago

Day 19 - 🚀 Mealy FSM Sequence Detector #100daysofDV #fsm

Day 19 - 🚀 Mealy FSM Sequence Detector #100daysofDV #fsm Explore VLSI

960 views - 7 months ago