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ASIC beauty shots - TT IHP 0p2 / 0p3 / 25A unboxing
Sylvain Munaut and Tiny Tapeout
382 views - 2 months ago
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![[stream] iCE40 Linux series: It's alive ! (4/4)](/thumb?url=http%3A%2F%2Finvidious%3A3000%2Fvi%2Fd-STNmJ0zrI%2Fmqdefault.jpg)
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![[stream] iCE40 Linux series: First signs of life (3/4)](/thumb?url=http%3A%2F%2Finvidious%3A3000%2Fvi%2FSYnD-D7BHoQ%2Fmqdefault.jpg)
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![[stream] iCE40 Linux series: Kernel boot process debug (2/4)](/thumb?url=http%3A%2F%2Finvidious%3A3000%2Fvi%2FuQ2EZsLEcl4%2Fmqdefault.jpg)
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![[stream] iCE40 Linux series: Initial Gateware (1/4)](/thumb?url=http%3A%2F%2Finvidious%3A3000%2Fvi%2FJSUnWPcpo2Q%2Fmqdefault.jpg)
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![[stream] Initial port of DooM to the Hackaday Superconference FPGA Badge](/thumb?url=http%3A%2F%2Finvidious%3A3000%2Fvi%2FVzbI6qFaTmQ%2Fmqdefault.jpg)
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![[stream] FPGA / iCE40 : Implementing a USB sound card on iCEbreaker-bitsy](/thumb?url=http%3A%2F%2Finvidious%3A3000%2Fvi%2FUD2h8IuLXCQ%2Fmqdefault.jpg)
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![[stream] iCE40 : Implementing a USB sound card on iCEbreaker-bitsy](/thumb?url=http%3A%2F%2Finvidious%3A3000%2Fvi%2F4-JE2nZt0sk%2Fmqdefault.jpg)
5:01:49
![[stream] Sky130 - Exploring OpenLANE and OpenDB to create a register file](/thumb?url=http%3A%2F%2Finvidious%3A3000%2Fvi%2FAT_LcmaCZmw%2Fmqdefault.jpg)
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![[stream] Skywater 130nm PDK - Initial Discovery](/thumb?url=http%3A%2F%2Finvidious%3A3000%2Fvi%2FgRYBdTXbxiU%2Fmqdefault.jpg)
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![[stream] USB test suite - Setup and retry/resend procedure testing](/thumb?url=http%3A%2F%2Finvidious%3A3000%2Fvi%2FjHbjioByjRY%2Fmqdefault.jpg)
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![[stream] iCE40 / FPGA IO timing analysis explanation and examples](/thumb?url=http%3A%2F%2Finvidious%3A3000%2Fvi%2FmitAhMOt3zI%2Fmqdefault.jpg)
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![[stream] iCE40: Running Micropython on iCEbreaker with HyperRAM](/thumb?url=http%3A%2F%2Finvidious%3A3000%2Fvi%2FDR4q45_hLvg%2Fmqdefault.jpg)
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![[stream] iCE40 cache part 5: Integration in PicoRV32 SoC + HW Testing](/thumb?url=http%3A%2F%2Finvidious%3A3000%2Fvi%2FSnzI0K8MI1s%2Fmqdefault.jpg)
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![[stream] iCE40 cache part 4: Failure modes, test bench and bus adapter to Wishbone](/thumb?url=http%3A%2F%2Finvidious%3A3000%2Fvi%2FYPQb5aL6rOA%2Fmqdefault.jpg)
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![[stream] iCE40 cache part 3: Erratas, EBR/SPRAM inner workings and the memory controller interface](/thumb?url=http%3A%2F%2Finvidious%3A3000%2Fvi%2FVV1PAIEx2vA%2Fmqdefault.jpg)
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![[stream] iCE40 cache part 2: Analyzing yosys synthesis result for the fast path](/thumb?url=http%3A%2F%2Finvidious%3A3000%2Fvi%2FxhzDrZiXrkc%2Fmqdefault.jpg)
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![[stream] iCE40 cache part 1: Requirement and fast path draft](/thumb?url=http%3A%2F%2Finvidious%3A3000%2Fvi%2FF_XvGUxu6ig%2Fmqdefault.jpg)
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