AK APT LOGICS

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RTL to GDSII Part 9: Installing Klayout & OpenTimer in Virtual Box

RTL to GDSII Part 9: Installing Klayout & OpenTimer in Virtual Box AK APT LOGICS

83 views - 1 month ago

#16 Design & Verification of NOR Gate | Verilog Switch Level Modelling | EDA Playground

#16 Design & Verification of NOR Gate | Verilog Switch Level Modelling | EDA Playground AK APT LOGICS

7 views - 1 month ago

C Programming Part 16: sizeof Operator in C | Memory Size of Data Types | %zu Explained | AK Apt

C Programming Part 16: sizeof Operator in C | Memory Size of Data Types | %zu Explained | AK Apt AK APT LOGICS

2 months ago

C Programming Part 15: Decimal Precision in C | %.f Format Specifier | Rounding Explained |

C Programming Part 15: Decimal Precision in C | %.f Format Specifier | Rounding Explained | AK APT LOGICS

2 views - 2 months ago

C Programming Part 14: Numeric Data Types | int vs float vs double | Scientific Notation |

C Programming Part 14: Numeric Data Types | int vs float vs double | Scientific Notation | AK APT LOGICS

2 months ago

#15 Design & Verification of NOR Gate | Verilog Behavioural Modelling | EDA Playground

#15 Design & Verification of NOR Gate | Verilog Behavioural Modelling | EDA Playground AK APT LOGICS

3 views - 2 months ago

#14 Design & Verification of NOR Gate | Verilog Dataflow Modelling | EDA Playground

#14 Design & Verification of NOR Gate | Verilog Dataflow Modelling | EDA Playground AK APT LOGICS

2 months ago

#13 Design & Verification of NOR Gate | Verilog Gate Level Modelling | EDA Playground

#13 Design & Verification of NOR Gate | Verilog Gate Level Modelling | EDA Playground AK APT LOGICS

2 months ago

#12 Design & Verification of AND Gate | Verilog Switch Level Modelling | EDA Playground

#12 Design & Verification of AND Gate | Verilog Switch Level Modelling | EDA Playground AK APT LOGICS

2 views - 2 months ago

#11 Design & Verification of AND Gate | Verilog Behavioural Modelling | EDA Playground

#11 Design & Verification of AND Gate | Verilog Behavioural Modelling | EDA Playground AK APT LOGICS

2 months ago

#10 Design & Verification of AND Gate | Verilog Dataflow Modelling | EDA Playground

#10 Design & Verification of AND Gate | Verilog Dataflow Modelling | EDA Playground AK APT LOGICS

2 months ago

#9 Design & Verification of AND Gate | Verilog Gate Level Modelling | EDA Playground

#9 Design & Verification of AND Gate | Verilog Gate Level Modelling | EDA Playground AK APT LOGICS

2 views - 2 months ago

Arduino Tutorial Part 7 | LDR Light Intensity Meter with LED Bar Graph and LCD

Arduino Tutorial Part 7 | LDR Light Intensity Meter with LED Bar Graph and LCD AK APT LOGICS

2 months ago

C Programming Part 13: The char Data Type | Single Characters vs. ASCII Values | AK Apt Logics

C Programming Part 13: The char Data Type | Single Characters vs. ASCII Values | AK Apt Logics AK APT LOGICS

2 views - 3 months ago

C Programming Part 12: Data Types & Format Specifiers | int, float, char, double

C Programming Part 12: Data Types & Format Specifiers | int, float, char, double AK APT LOGICS

3 views - 3 months ago

C Programming Part 11: Master C Identifiers | Variable Naming Rules & Best Practices

C Programming Part 11: Master C Identifiers | Variable Naming Rules & Best Practices AK APT LOGICS

2 views - 3 months ago

#8 Design & Verification of NAND Gate | Verilog Switch Level Modelling | EDA Playground |

#8 Design & Verification of NAND Gate | Verilog Switch Level Modelling | EDA Playground | AK APT LOGICS

8 views - 3 months ago

C Programming Part 10: Declaring Multiple Variables | Efficiency vs. Readability | AK Apt Logics

C Programming Part 10: Declaring Multiple Variables | Efficiency vs. Readability | AK Apt Logics AK APT LOGICS

2 views - 3 months ago

SystemVerilog Part 2: The 4-State Logic System | 0, 1, X, Z Explained | AK Apt Logics

SystemVerilog Part 2: The 4-State Logic System | 0, 1, X, Z Explained | AK Apt Logics AK APT LOGICS

6 views - 3 months ago

C Programming Part 9: Changing & Assigning Variable Values | Re-assignment & Constants | AK

C Programming Part 9: Changing & Assigning Variable Values | Re-assignment & Constants | AK AK APT LOGICS

4 views - 3 months ago

#7 Design & Verification of NAND Gate | Verilog Behavioural Modelling | EDA Playground |

#7 Design & Verification of NAND Gate | Verilog Behavioural Modelling | EDA Playground | AK APT LOGICS

7 views - 3 months ago

RTL to GDSII Part 8: Verifying VLSI Tool Installation (Yosys, Magic & GrayWolf) ✅

RTL to GDSII Part 8: Verifying VLSI Tool Installation (Yosys, Magic & GrayWolf) ✅ AK APT LOGICS

106 views - 3 months ago

RTL to GDSII Part 7: Cloning vsdflow from GitHub to your Linux Environment

RTL to GDSII Part 7: Cloning vsdflow from GitHub to your Linux Environment AK APT LOGICS

139 views - 3 months ago

RTL to GDSII Part 6: How to Increase VirtualBox Linux Screen Resolution & Window Size 🐧💻

RTL to GDSII Part 6: How to Increase VirtualBox Linux Screen Resolution & Window Size 🐧💻 AK APT LOGICS

91 views - 3 months ago

RTL to GDSII Part 5: Linux Environment Ready! ✅ Final Check & Verification

RTL to GDSII Part 5: Linux Environment Ready! ✅ Final Check & Verification AK APT LOGICS

84 views - 3 months ago

RTL to GDSII Part 4: Setting Up the Linux Environment & Tool Prerequisites 🐧💻

RTL to GDSII Part 4: Setting Up the Linux Environment & Tool Prerequisites 🐧💻 AK APT LOGICS

182 views - 3 months ago

RTL to GDSII Part 3: Setting Up VirtualBox & Optimizing for OpenLane VLSI

RTL to GDSII Part 3: Setting Up VirtualBox & Optimizing for OpenLane VLSI AK APT LOGICS

179 views - 3 months ago

RTL to GDSII Part 2: Step-by-Step Linux Ubuntu Installation & Setup for VLSI

RTL to GDSII Part 2: Step-by-Step Linux Ubuntu Installation & Setup for VLSI AK APT LOGICS

192 views - 3 months ago

RTL to GDSII Part 1: How to Install Oracle VirtualBox for VLSI Tools

RTL to GDSII Part 1: How to Install Oracle VirtualBox for VLSI Tools AK APT LOGICS

505 views - 3 months ago

C Programming Part 8: Format Specifiers in C | printf() Secrets & ASCII Basics | AK Apt Logics

C Programming Part 8: Format Specifiers in C | printf() Secrets & ASCII Basics | AK Apt Logics AK APT LOGICS

3 views - 3 months ago

#6 Design and Verification of Nand gate using Verilog Dataflow Modelling using EDA Playground

#6 Design and Verification of Nand gate using Verilog Dataflow Modelling using EDA Playground AK APT LOGICS

4 views - 4 months ago

#5 Design and Verification of Nand gate using Verilog gate Level Modelling in Eda Playground

#5 Design and Verification of Nand gate using Verilog gate Level Modelling in Eda Playground AK APT LOGICS

7 views - 4 months ago

C Programming Example 6: Check if Two Numbers are Equal or Not | If-Else Logic | AK Apt Logics

C Programming Example 6: Check if Two Numbers are Equal or Not | If-Else Logic | AK Apt Logics AK APT LOGICS

6 views - 4 months ago

C Programming Part 7: Variables in C | Declaration, Initialization & Rules | AK Apt Logics

C Programming Part 7: Variables in C | Declaration, Initialization & Rules | AK Apt Logics AK APT LOGICS

4 months ago

SystemVerilog Part 1: Comments in SystemVerilog | Single-line & Multi-line | AK Apt Logics

SystemVerilog Part 1: Comments in SystemVerilog | Single-line & Multi-line | AK Apt Logics AK APT LOGICS

14 views - 4 months ago

#4 Design and Verification of Not gate in Verilog Switch Level Modelling using eda playground

#4 Design and Verification of Not gate in Verilog Switch Level Modelling using eda playground AK APT LOGICS

7 views - 4 months ago

#3 Design and Verification of Not gate in Verilog Behavioural Modelling using Eda Playground

#3 Design and Verification of Not gate in Verilog Behavioural Modelling using Eda Playground AK APT LOGICS

8 views - 4 months ago

#2 Design and Verification of Not gate in Verilog Data flow Modelling using Eda Playground

#2 Design and Verification of Not gate in Verilog Data flow Modelling using Eda Playground AK APT LOGICS

7 views - 4 months ago

#1 Design and Verification of Not gate in Verilog gate level modelling using Eda Playground

#1 Design and Verification of Not gate in Verilog gate level modelling using Eda Playground AK APT LOGICS

37 views - 4 months ago

C Programming Part 6 C Comments Single Line Multi Line Explained

C Programming Part 6 C Comments Single Line Multi Line Explained AK APT LOGICS

4 months ago

C Programming Example 5 Find Largest Among Three Numbers 4 Methods

C Programming Example 5 Find Largest Among Three Numbers 4 Methods AK APT LOGICS

4 months ago

Python Programming Part 11 Numbers Data Types Complete Guide

Python Programming Part 11 Numbers Data Types Complete Guide AK APT LOGICS

2 views - 4 months ago

C Programming Example 4 Check Positive Negative or Zero

C Programming Example 4 Check Positive Negative or Zero AK APT LOGICS

4 months ago

C Programming Example 3: Sum of Even and Odd Numbers (1 to N)

C Programming Example 3: Sum of Even and Odd Numbers (1 to N) AK APT LOGICS

4 months ago

C Programming Example 2: Check Even or Odd Number (3 Different Methods)

C Programming Example 2: Check Even or Odd Number (3 Different Methods) AK APT LOGICS

4 months ago

C Programming Part 4 | printf() Output & Double Quotes Explained

C Programming Part 4 | printf() Output & Double Quotes Explained AK APT LOGICS

4 months ago

C Programming Part 3 | C Statements Explained (With Examples)

C Programming Part 3 | C Statements Explained (With Examples) AK APT LOGICS

3 views - 4 months ago

C Programming Example 1: Hello World (2 Different Methods)

C Programming Example 1: Hello World (2 Different Methods) AK APT LOGICS

9 views - 4 months ago

VHDL Tutorial Part 5 | Structural Model in VHDL

VHDL Tutorial Part 5 | Structural Model in VHDL AK APT LOGICS

15 views - 6 months ago

VHDL Tutorial Part 4 | Dataflow Model in VHDL

VHDL Tutorial Part 4 | Dataflow Model in VHDL AK APT LOGICS

6 views - 6 months ago

VHDL Tutorial Part 3 | Behavioral Model in VHDL

VHDL Tutorial Part 3 | Behavioral Model in VHDL AK APT LOGICS

11 views - 6 months ago

VHDL Tutorial Part 2 | Architecture Declaration in VHDL

VHDL Tutorial Part 2 | Architecture Declaration in VHDL AK APT LOGICS

8 views - 6 months ago

VHDL Tutorial Part 1 | Introduction to VHDL Programming

VHDL Tutorial Part 1 | Introduction to VHDL Programming AK APT LOGICS

66 views - 6 months ago

Python Programming Part 10 | Data Types in Python Complete Guide

Python Programming Part 10 | Data Types in Python Complete Guide AK APT LOGICS

3 views - 6 months ago

Python Programming Part 8 | Output Variables with Print Function

Python Programming Part 8 | Output Variables with Print Function AK APT LOGICS

6 months ago

Python Programming Part 7 | Multiple Variables and Unpacking

Python Programming Part 7 | Multiple Variables and Unpacking AK APT LOGICS

6 months ago

Python Programming Part 9 | Global and Local Variables Explained

Python Programming Part 9 | Global and Local Variables Explained AK APT LOGICS

6 months ago

Python Programming Part 6 | Variable Naming Rules & Best Practices

Python Programming Part 6 | Variable Naming Rules & Best Practices AK APT LOGICS

4 views - 7 months ago

Python Programming Part 5 | Variables in Python Explained

Python Programming Part 5 | Variables in Python Explained AK APT LOGICS

5 views - 7 months ago

Python Programming Part 4 | Python Comments – Single-line & Multiline

Python Programming Part 4 | Python Comments – Single-line & Multiline AK APT LOGICS

7 views - 7 months ago