Prasanna_VLSI_KT

@UCz6nS5wbt41e8BvB7DiPgnQ - 100 subscribers

Welcome to my YouTube channel! I'm a PhD graduate from IIT Roorkee with expertise in VLSI, chip tape-outs, and multiple EDA tools. Currently working as a System/SoC Architect for MCUs at STMicroelectronics, I created this channel to share my knowledge and experience in the VLSI field. Join me for insights, tutorials, and real-world applications that bridge the gap between theory and practice in digital design.

Home Videos Live Playlists

V0. Intro Video of Verilog HDL Course: Real-Life Applications and VLSI Career Insights

V0. Intro Video of Verilog HDL Course: Real-Life Applications and VLSI Career Insights Prasanna_VLSI_KT

385 views - 1 year ago

V23. User-Defined Primitives and Verilog Tasks & Functions: Practical Examples

V23. User-Defined Primitives and Verilog Tasks & Functions: Practical Examples Prasanna_VLSI_KT

202 views - 1 year ago

V22. CMOS Design in Verilog HDL: Inverter, Gates, MUX, Latch, and Delay Models

V22. CMOS Design in Verilog HDL: Inverter, Gates, MUX, Latch, and Delay Models Prasanna_VLSI_KT

142 views - 1 year ago

V21. Exploring Switch-Level Modeling in Verilog HDL: MOS and Bi-Directional Switches

V21. Exploring Switch-Level Modeling in Verilog HDL: MOS and Bi-Directional Switches Prasanna_VLSI_KT

417 views - 1 year ago

V20. Live Verilog Coding: Behavioral Modeling with Non-Synthesizable Delays and For Loop Analysis

V20. Live Verilog Coding: Behavioral Modeling with Non-Synthesizable Delays and For Loop Analysis Prasanna_VLSI_KT

22 views - 1 year ago

V19. Advanced Verilog HDL: Loop Examples, Block Structures, and Practical Designs

V19. Advanced Verilog HDL: Loop Examples, Block Structures, and Practical Designs Prasanna_VLSI_KT

30 views - 1 year ago

V18. Verilog HDL Essentials: Conditional Statements, Multiway Branching, and Loops

V18. Verilog HDL Essentials: Conditional Statements, Multiway Branching, and Loops Prasanna_VLSI_KT

99 views - 1 year ago

V17. Live Verilog Coding: Clock Divider Techniques and FPGA Delay Implementation

V17. Live Verilog Coding: Clock Divider Techniques and FPGA Delay Implementation Prasanna_VLSI_KT

360 views - 1 year ago

V16. Mastering Event-Based Timing Control in Verilog HDL: Live Coding Blocking vs Non-Blocking ex.

V16. Mastering Event-Based Timing Control in Verilog HDL: Live Coding Blocking vs Non-Blocking ex. Prasanna_VLSI_KT

95 views - 1 year ago

V13. Live Coding Verilog: Multiplexer with Assign Statements, exploring the implications of scaling

V13. Live Coding Verilog: Multiplexer with Assign Statements, exploring the implications of scaling Prasanna_VLSI_KT

14 views - 1 year ago

V12. Live Coding with Verilog: Data Flow Operators and FPGA Resource Utilization Insights

V12. Live Coding with Verilog: Data Flow Operators and FPGA Resource Utilization Insights Prasanna_VLSI_KT

16 views - 1 year ago

V10. Understanding the Four Types of Modeling in Verilog

V10. Understanding the Four Types of Modeling in Verilog Prasanna_VLSI_KT

14 views - 1 year ago

V9. Live Verilog coding: 4-Bit Ripple Carry Adder: Synthesis and FPGA Signal Flow Analysis

V9. Live Verilog coding: 4-Bit Ripple Carry Adder: Synthesis and FPGA Signal Flow Analysis Prasanna_VLSI_KT

92 views - 1 year ago

V15. Advanced Behavioral Modeling in Verilog HDL: Blocking vs Non-Blocking Assignments

V15. Advanced Behavioral Modeling in Verilog HDL: Blocking vs Non-Blocking Assignments Prasanna_VLSI_KT

35 views - 1 year ago

V14. Behavioral Modeling in Verilog HDL: Timing Control and Procedural Assignments

V14. Behavioral Modeling in Verilog HDL: Timing Control and Procedural Assignments Prasanna_VLSI_KT

49 views - 1 year ago

V11. Digital Design with Verilog HDL: Exploring Data Flow Modeling and Assign Statements

V11. Digital Design with Verilog HDL: Exploring Data Flow Modeling and Assign Statements Prasanna_VLSI_KT

13 views - 1 year ago

V8. Live Verilog Coding: Gate-Level Modeling with Test Benches and FPGA Comparisons

V8. Live Verilog Coding: Gate-Level Modeling with Test Benches and FPGA Comparisons Prasanna_VLSI_KT

15 views - 1 year ago

V7. Digital Design with Verilog HDL: Gate-Level Modeling and Logic Gate Primitives

V7. Digital Design with Verilog HDL: Gate-Level Modeling and Logic Gate Primitives Prasanna_VLSI_KT

49 views - 1 year ago

V6. Live Verilog Coding: Ripple Carry Adder Simulation and FPGA Implementation on Zed Board

V6. Live Verilog Coding: Ripple Carry Adder Simulation and FPGA Implementation on Zed Board Prasanna_VLSI_KT

73 views - 1 year ago

V5. Live Verilog Coding in Vivado: Basics, Data Types, and SR Latch Simulation

V5. Live Verilog Coding in Vivado: Basics, Data Types, and SR Latch Simulation Prasanna_VLSI_KT

86 views - 1 year ago

V4. Hands-On Digital Design with Verilog HDL: Exploring Modules, Ports, and More Part 2

V4. Hands-On Digital Design with Verilog HDL: Exploring Modules, Ports, and More Part 2 Prasanna_VLSI_KT

65 views - 1 year ago

V3. Hands-On Digital Design with Verilog HDL: Exploring Modules, Ports, and More

V3. Hands-On Digital Design with Verilog HDL: Exploring Modules, Ports, and More Prasanna_VLSI_KT

90 views - 1 year ago

V2. Hands-On Digital Circuit Design: From Logic Gates to Real-World Applications - Part 1

V2. Hands-On Digital Circuit Design: From Logic Gates to Real-World Applications - Part 1 Prasanna_VLSI_KT

104 views - 1 year ago

V1. Hands-On Digital Circuit Design: From Logic Gates to Real-World Applications - Part 1

V1. Hands-On Digital Circuit Design: From Logic Gates to Real-World Applications - Part 1 Prasanna_VLSI_KT

132 views - 1 year ago